[PATCH 16/62] ARM: dts: r8a7743: Add PCIe Controller device node


Biju Das <biju.das@...>
 

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 4c5c952e61190e5a0e06128156eef84d290a0045)
(updated clocks, power-domains property and removed reset property)
Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
---
arch/arm/boot/dts/r8a7743.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 767b7fe..fccd70c 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -1429,6 +1429,33 @@
phy-names = "usb";
};
};
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7743",
+ "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+ 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7743_CLK_PCIEC>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
};

/* External root clock */
--
2.7.4

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