[PATCH/RFC 4.19.y-cip v2 31/51] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N


Fabrizio Castro <fabrizio.castro@...>
 

From: Takeshi Kihara <takeshi.kihara.df@...>

commit 943ff71281c6ce44ca48ea1b08c55f1e63648d00 upstream.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and
NFRB_N_A pin functions are selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index a3f22ff..fba0c22 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1037,7 +1037,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),

PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
- PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
+ PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDFC_0),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
@@ -1046,7 +1046,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),

PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
- PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
+ PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
--
2.7.4

Join cip-dev@lists.cip-project.org to automatically receive all group messages.