Hello Pavel, Hayashi-san, Jan, Daniel,
Addressing this email to all of you as both RT and CIP Core are involved.
I started to look into RT testing in more detail today.
I've created an RT configuration for the RZ/G1 boards:
I'll do something similar for the RZ/G2 boards soon.
Built it with linux-4.4.y-cip-rt and run cyclic test:
Times look okay to an rt-untrained eye:
T: 0 ( 1169) P:98 I:1000 C: 59993 Min: 13 Act: 16 Avg: 16 Max: 33
Compared to a run with linux-4.4.y-cip:
T: 0 ( 938) P:98 I:1000 C: 6000 Min: 1618 Act: 9604 Avg: 9603 Max: 14550
Pavel, does the above look okay/useful to you? Or is cyclictest not worth running unless there is some load on the system?
Currently there is an issue with the way that the cyclic test case results are shown (i.e. they aren't) in LAVA due to a change  made to Linaro's cyclictest.sh.
That means that the test parsing now depends on Python, which isn't included in the cip-core RFS  that is currently being used.
Do either of the CIP Core profiles include Python support?
Linaro test-definitions  have the following tests marked within the preempt-rt scope:
Which of the above would be valuable to run on CIP RT Kernels?
A while back Daniel Wagner also did some work on a Jitterdebugger test , but it hasn't been merged yet and I'm not sure what the current status is. Any updates Daniel?
Is anyone able to provide RT config/defconfigs for the x86 and arm boards in the Mentor lab? Or BBB, QEMU etc.? (assuming that the hardware is suitable).
Kind regards, Chris