From: Biju Das <biju.das@...>

commit 8438bfda9d76815707a7823ab91a944eea6d6266 upstream.

Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

Based on the work done by Dien Pham <dien.pham.ry@...>
and others for r8a77990 SoC.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Link: https://lore.kernel.org/r/1568364608-46548-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[fab: changed oder of cpu-thermal children according to order upstream]
Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 354d6b9..0c57e15 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -73,6 +73,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
device_type = "cpu";
+ #cooling-cells = <2>;
power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
@@ -1899,18 +1900,30 @@
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&thermal>;
+ polling-delay = <0>;
+ thermal-sensors = <&thermal 0>;
+ sustainable-power = <717>;
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
+ };
+ };

trips {
- cpu-crit {
+ sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
- };

- cooling-maps {
+ target: trip-point1 {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
};
};
};
--
2.7.4