[PATCH 4.4.y-cip 02/10] ARM: dts: r8a7742: Add IRQC support


Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>

commit a31a8c9cbc0762b096e0b176ba481a60e54db5bf upstream.

Describe the IRQC interrupt controller in the r8a7742 device tree.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Acked-by: Marc Zyngier <maz@...>
Link: https://lore.kernel.org/r/1588794695-27852-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
[biju: changed clocks and power-domains properties, removed resets property]
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm/boot/dts/r8a7742.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 9e26313e09e1..d128fa1d4847 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -700,6 +700,19 @@
reg = <0 0xe6160000 0 0x0100>;
};

+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7742", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7742_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
+ };
+
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
--
2.17.1

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