[PATCH 4.4.y-cip 11/11] ARM: dts: am33xx: Add updated operating-points-v2 table for cpu


Chen-Yu Tsai (Moxa) <wens@...>
 

From: Dave Gerlach <d-gerlach@...>

commit 72ac40fcb164a3d8fbd1ff13647abe67df26ced5 upstream.

After the ti-cpufreq driver has been added, we can now drop the
operating-points table present in am33xx.dtsi for the cpu and add an
operating-points-v2 table with all OPPs available for all silicon
revisions. Also add necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime as part of the operating-points
table.

Information from AM335x Data Manual, SPRS717i, Revised December 2015,
Table 5-7.

Signed-off-by: Dave Gerlach <d-gerlach@...>
Reviewed-by: Lukasz Majewski <lukma@...>
Acked-by: Viresh Kumar <viresh.kumar@...>
Signed-off-by: Tony Lindgren <tony@...>
Signed-off-by: Chen-Yu Tsai (Moxa) <wens@...>
---
arch/arm/boot/dts/am33xx.dtsi | 87 +++++++++++++++++++++++++++++------
1 file changed, 74 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dts=
i
index 4b40e6d401a03..c256718d75801 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -45,19 +45,7 @@
device_type =3D "cpu";
reg =3D <0>;
=20
- /*
- * To consider voltage drop between PMIC and SoC,
- * tolerance value is reduced to 2% from 4% and
- * voltage value is increased as a precaution.
- */
- operating-points =3D <
- /* kHz uV */
- 720000 1285000
- 600000 1225000
- 500000 1125000
- 275000 1125000
- >;
- voltage-tolerance =3D <2>; /* 2 percentage */
+ operating-points-v2 =3D <&cpu0_opp_table>;
=20
clocks =3D <&dpll_mpu_ck>;
clock-names =3D "cpu";
@@ -66,6 +54,79 @@
};
};
=20
+ cpu0_opp_table: opp-table {
+ compatible =3D "operating-points-v2-ti-cpu";
+ syscon =3D <&scm_conf>;
+
+ /*
+ * The three following nodes are marked with opp-suspend
+ * because the can not be enabled simultaneously on a
+ * single SoC.
+ */
+ opp50@300000000 {
+ opp-hz =3D /bits/ 64 <300000000>;
+ opp-microvolt =3D <950000 931000 969000>;
+ opp-supported-hw =3D <0x06 0x0010>;
+ opp-suspend;
+ };
+
+ opp100@275000000 {
+ opp-hz =3D /bits/ 64 <275000000>;
+ opp-microvolt =3D <1100000 1078000 1122000>;
+ opp-supported-hw =3D <0x01 0x00FF>;
+ opp-suspend;
+ };
+
+ opp100@300000000 {
+ opp-hz =3D /bits/ 64 <300000000>;
+ opp-microvolt =3D <1100000 1078000 1122000>;
+ opp-supported-hw =3D <0x06 0x0020>;
+ opp-suspend;
+ };
+
+ opp100@500000000 {
+ opp-hz =3D /bits/ 64 <500000000>;
+ opp-microvolt =3D <1100000 1078000 1122000>;
+ opp-supported-hw =3D <0x01 0xFFFF>;
+ };
+
+ opp100@600000000 {
+ opp-hz =3D /bits/ 64 <600000000>;
+ opp-microvolt =3D <1100000 1078000 1122000>;
+ opp-supported-hw =3D <0x06 0x0040>;
+ };
+
+ opp120@600000000 {
+ opp-hz =3D /bits/ 64 <600000000>;
+ opp-microvolt =3D <1200000 1176000 1224000>;
+ opp-supported-hw =3D <0x01 0xFFFF>;
+ };
+
+ opp120@720000000 {
+ opp-hz =3D /bits/ 64 <720000000>;
+ opp-microvolt =3D <1200000 1176000 1224000>;
+ opp-supported-hw =3D <0x06 0x0080>;
+ };
+
+ oppturbo@720000000 {
+ opp-hz =3D /bits/ 64 <720000000>;
+ opp-microvolt =3D <1260000 1234800 1285200>;
+ opp-supported-hw =3D <0x01 0xFFFF>;
+ };
+
+ oppturbo@800000000 {
+ opp-hz =3D /bits/ 64 <800000000>;
+ opp-microvolt =3D <1260000 1234800 1285200>;
+ opp-supported-hw =3D <0x06 0x0100>;
+ };
+
+ oppnitro@1000000000 {
+ opp-hz =3D /bits/ 64 <1000000000>;
+ opp-microvolt =3D <1325000 1298500 1351500>;
+ opp-supported-hw =3D <0x04 0x0200>;
+ };
+ };
+
pmu {
compatible =3D "arm,cortex-a8-pmu";
interrupts =3D <3>;
--=20
2.28.0

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