Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}


Lad Prabhakar
 

Hi Nobuhiro,

-----Original Message-----
From: nobuhiro1.iwamatsu@... <nobuhiro1.iwamatsu@...>
Sent: 30 October 2020 10:58
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>; pavel@...
Cc: cip-dev@...; Biju Das <biju.das.jz@...>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Prabhakar,

-----Original Message-----
From: Prabhakar Mahadev Lad [mailto:prabhakar.mahadev-lad.rj@...]
Sent: Thursday, October 29, 2020 12:36 AM
To: Pavel Machek <pavel@...>
Cc: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@...>; Biju Das <biju.das.jz@...>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>; Biju Das
<biju.das.jz@...>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fcip-
dev%2F&amp;data=04%7C01%7Cprabhakar.mahadev-
lad.rj%40bp.renesas.com%7C55e2a70e90c54aed478908d87cc2ab6c%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637396522
837081719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;
sdata=P4d9zKypm%2B0kGpmD32bPiC2W6SXLX5Fp%2Fm99bwzb6Y8%3D&amp;reserved=0
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled
as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.
OK.


Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)
Thank you for attaching the test results.
I will apply and push this series.
Thank you.

Cheers,
Prabhakar

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