Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Pavel Machek


These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.

Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also
lspci output)
Thank you!

Best regards,


DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Join { to automatically receive all group messages.