Hi All,

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

Patches add support for the following:
* Documentation for RZ/G2{L,LC,UL} SoC variants
* Documentation for Renesas SMARC EVK
* SYSC binding doc required for SoC identification
* SoC identification support
* Enabling ARCH_R9A07G044 in defconfig

All the patches have been cherry picked from v5.16-rc5

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual-
core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit

Cheers,
Prabhakar


Lad Prabhakar (7):
dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC
dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants
dt-bindings: arm: renesas: Document SMARC EVK
dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation
for SYSC controller
soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's
soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC}
SoC's
arm64: defconfig: Enable ARCH_R9A07G044

.../devicetree/bindings/arm/renesas.yaml | 18 ++++++
.../bindings/power/renesas,rzg2l-sysc.yaml | 63 +++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/soc/renesas/Kconfig | 5 ++
drivers/soc/renesas/renesas-soc.c | 33 +++++++++-
5 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml

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2.17.1