-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: 17 December 2021 10:19
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>; Biju Das <biju.das.jz@...>
Subject: Re: [PATCH 5.10.y-cip 11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's

Hi!

commit 68a45525297b2e9afbd9bba807ddd2c9f69beee6 upstream.

Add initial DTSI for RZ/G2{L,LC} SoC's.

File structure:
r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi =>
RZ/G2L R9A07G044L1 SoC specific parts r9a07g044l2.dtsi => RZ/G2L
R9A07G044L2 SoC specific parts

I just want to double check:

+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";

Are the last two interrupts supposed to be same?

Best regards,
Pavel
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