Re: [PATCH 5.10.y-cip 23/24] clk: renesas: rzg2l: Add support to handle coupled clocks


Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: 17 December 2021 10:38
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>; Biju Das <biju.das.jz@...>
Subject: Re: [PATCH 5.10.y-cip 23/24] clk: renesas: rzg2l: Add support to handle coupled clocks

Hi!

From: Biju Das <biju.das.jz@...>

commit 32897e6fff196a5de4981030466ae391dfe56c7b upstream.

The AXI and CHI clocks use the same register bit for controlling clock
output. Add a new clock type for coupled clocks, which sets the
CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and
clears the bit only when both clocks are disabled.
So the clocks can have different properties (frequency?), but can only be enabled/disabled together?
So we can't handle them as one clock?
Since there are two clock lines going to the IP with different parents and just one bit to handle this, for this reason its implemented as coupled clock.

Cheers,
Prabhakar

Best regards,
Pavel
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