Hi all,

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@denx.de>

I pushed this series.

Best regards,
Nobuhiro
________________________________________
差出人: Pavel Machek
送信: 2021 12 月 17 日 (金曜日) 19:39
宛先: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
Cc: cip-dev@lists.cip-project.org; pavel@denx.de; biju.das.jz@bp.renesas.com
件名: Re: [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK


Hi!

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
   - CPU
   - CPG
   - GIC
* Initial device tree for RZ/G2L SMARC EVK
   - memory
   - External input clock
   - SCIF

All the patches have been cherry picked from 5.16-rc5. For testing purpose
MR [0] can be used.

I will check this series, and I am also checking the build.

https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/431663140

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@denx.de>
                                                                Pavel
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