-----Original Message-----
From: cip-dev@... <cip-dev@...> On Behalf Of Nobuhiro Iwamatsu via
lists.cip-project.org
Sent: 20 December 2021 04:47
To: pavel@...
Cc: cip-dev@...; Biju Das <biju.das.jz@...>
Subject: Re: [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC +
SMARC EVK

Hi all,

Thank you. I checked the series and only found some details (some of
them were fixed later in the series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@...>

I pushed this series.

Best regards,
Nobuhiro
________________________________________
差出人: Pavel Machek
送信: 2021 12 月 17 日 (金曜日) 19:39
宛先: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
Cc: cip-dev@...; pavel@...; biju.das.jz@...
件名: Re: [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC
EVK


Hi!

This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
   - CPU
   - CPG
   - GIC
* Initial device tree for RZ/G2L SMARC EVK
   - memory
   - External input clock
   - SCIF

All the patches have been cherry picked from 5.16-rc5. For testing
purpose MR [0] can be used.

I will check this series, and I am also checking the build.

https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi
tlab.com%2Fcip-project%2Fcip-kernel%2Flinux-cip%2F-%2Fpipelines%2F43
1663140&amp;data=04%7C01%7Cprabhakar.mahadev-lad.rj%40bp.renesas.com
%7C0236577471e44bed54b408d9c373d037%7C53d82571da1947e49cb4625a166a4a
2a%7C0%7C0%7C637755724454272916%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w
LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sd
ata=Qi4T0V5FPTCMF5tE5D1G%2BgkU5zTkTNU4MDxtwC9Yy8E%3D&amp;reserved=0

Thank you. I checked the series and only found some details (some of them were fixed later in the
series). I believe we can apply it.

Reviewed-by: Pavel Machek <pavel@...>
                                                                Pavel
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