Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter


Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: 30 December 2021 10:55
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>; Pavel Machek
<pavel@...>; Biju Das <biju.das.jz@...>
Subject: Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel
configuration parameter

Hi!

From: Biju Das <biju.das.jz@...>

commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream.

The DMAC on RZ/G2L has specific slave channel configuration parameters
for SSI.
This patch updates the dmas description and example node to include
the encoded slave channel configuration.
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -48,6 +48,24 @@ properties:
dmas:
minItems: 1
maxItems: 2
+ description:
+ The first cell represents a phandle to dmac
+ The second cell specifies the encoded MID/RID values of the SSI port
+ connected to the DMA client and the slave channel configuration
+ parameters.
+ bits[0:9] - Specifies MID/RID value of a SSI channel as below
+ MID/RID value of SSI rx0 = 0x256
+ MID/RID value of SSI tx0 = 0x255
+ MID/RID value of SSI rx1 = 0x25a
+ MID/RID value of SSI tx1 = 0x259
+ MID/RID value of SSI rt2 = 0x25f
+ MID/RID value of SSI rx3 = 0x262
+ MID/RID value of SSI tx3 = 0x261
+ bit[10] - HIEN = 1, Detects a request in response to the rising edge
+ of the signal
+ bit[11] - LVL = 0, Detects based on the edge
+ bits[12:14] - AM = 2, Bus cycle mode
+ bit[15] - TM = 0, Single transfer mode
I wish there was better solution to this. Device tree sources are quite human-readable, this really is
not.
Do agree!

Cheers,
Prabhakar

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