From: Biju Das <biju.das.jz@...>

commit 3d6b24a2ada3d53f7da9362d03856bdec74806e5 upstream.

This patch enables Receive/Transmit port of TOE and removes
the setting of promiscuous bit from EMAC configuration mode register.

This patch also update EMAC configuration mode comment from
"PAUSE prohibition" to "EMAC Mode: PAUSE prohibition; Duplex; TX;
RX; CRC Pass Through".

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Sergey Shtylyov <s.shtylyov@...>
Signed-off-by: Jakub Kicinski <kuba@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
---
drivers/net/ethernet/renesas/ravb.h | 6 ++++++
drivers/net/ethernet/renesas/ravb_main.c | 5 +++--
2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 5d07732ef35a..0b5801f7e961 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -204,6 +204,7 @@ enum ravb_reg {
TLFRCR = 0x0758,
RFCR = 0x0760,
MAFCR = 0x0778,
+ CSR0 = 0x0800, /* RZ/G2L only */
};


@@ -964,6 +965,11 @@ enum CXR31_BIT {
CXR31_SEL_LINK1 = 0x00000008,
};

+enum CSR0_BIT {
+ CSR0_TPE = 0x00000010,
+ CSR0_RPE = 0x00000020,
+};
+
#define DBAT_ENTRY_NUM 22
#define RX_QUEUE_OFFSET 4
#define NUM_RX_QUEUE 2
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index a02ea91c81f5..dc639ff1a395 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -517,10 +517,10 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)
/* Receive frame limit set register */
ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);

- /* PAUSE prohibition */
+ /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
ECMR_TE | ECMR_RE | ECMR_RCPT |
- ECMR_TXF | ECMR_RXF | ECMR_PRM, ECMR);
+ ECMR_TXF | ECMR_RXF, ECMR);

ravb_set_rate_gbeth(ndev);

@@ -532,6 +532,7 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)

/* E-MAC status register clear */
ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
+ ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);

/* E-MAC interrupt enable register */
ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
--
2.17.1