-----Original Message-----
From: Pavel Machek <pavel@...>
Sent: 05 April 2022 20:01
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...>
Cc: cip-dev@...; Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@...>; Pavel Machek <pavel@...>; Biju Das
<biju.das.jz@...>
Subject: Re: [PATCH 5.10.y-cip 23/29] clk: renesas: r9a07g044: Rename
CLK_PLL3_DIV4 macro

Hi!

Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock
tree mentioned in the hardware manual(Rev.1.00 Sep, 2021).

Changelog says rename,

@@ -106,9 +106,9 @@ static const struct cpg_core_clk

r9a07g044_core_clks[] __initconst = {

DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),

DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1,

2),

- DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,

but macro arguments are changed, so I want to make sure it was intended.

Best regards,
Pavel
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