[PATCH v2 5.10.y-cip 04/12] thermal/drivers/rz2gl: Fix OTP Calibration Register values


Biju Das
 

commit 2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6 upstream.

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM) indicates
whether bit [11:0] of OTPTSUTRIM is valid or invalid.

This patch updates the code to reflect this change.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/20220428093346.7552-1-biju.das.jz@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/thermal/rzg2l_thermal.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c
index a4c22123ad81..3e0e2e4fe27d 100644
--- a/drivers/thermal/rzg2l_thermal.c
+++ b/drivers/thermal/rzg2l_thermal.c
@@ -32,6 +32,8 @@
#define TSU_SS 0x10

#define OTPTSUTRIM_REG(n) (0x18 + ((n) * 0x4))
+#define OTPTSUTRIM_EN_MASK BIT(31)
+#define OTPTSUTRIM_MASK GENMASK(11, 0)

/* Sensor Mode Register(TSU_SM) */
#define TSU_SM_EN_TS BIT(0)
@@ -183,11 +185,15 @@ static int rzg2l_thermal_probe(struct platform_device *pdev)
pm_runtime_get_sync(dev);

priv->calib0 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0));
- if (!priv->calib0)
+ if (priv->calib0 & OTPTSUTRIM_EN_MASK)
+ priv->calib0 &= OTPTSUTRIM_MASK;
+ else
priv->calib0 = SW_CALIB0_VAL;

priv->calib1 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(1));
- if (!priv->calib1)
+ if (priv->calib1 & OTPTSUTRIM_EN_MASK)
+ priv->calib1 &= OTPTSUTRIM_MASK;
+ else
priv->calib1 = SW_CALIB1_VAL;

platform_set_drvdata(pdev, priv);
--
2.25.1

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