[PATCH 5.10.y-cip 09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC


Biju Das
 

commit 678eb67513a963e5ce00a4ed6a07a5722bd1267e upstream.

Document the device tree binding for the Renesas RZ/V2L SoC.

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Acked-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../bindings/clock/renesas,rzg2l-cpg.yaml | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 30b2e3d0d25d..bd3af8fc616b 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,13 +4,13 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

-title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode

maintainers:
- Geert Uytterhoeven <geert+renesas@...>

description: |
- On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
+ On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.

They provide the following functionalities:
@@ -22,7 +22,9 @@ description: |

properties:
compatible:
- const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ enum:
+ - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ - renesas,r9a07g054-cpg # RZ/V2L

reg:
maxItems: 1
@@ -40,9 +42,9 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- <dt-bindings/clock/r9a07g044-cpg.h>
+ <dt-bindings/clock/r9a07g*-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
- a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
+ a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 2

'#power-domain-cells':
@@ -56,7 +58,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
- the <dt-bindings/clock/r9a07g044-cpg.h>.
+ the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 1

required:
--
2.25.1

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