[PATCH 5.10.y-cip 12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic


Biju Das
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 29db30c45f07c929c86c40a5b85f18b69c89c638 upstream.

"a * (1 << b)" == "a << b".

No change in generated code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/clk/renesas/rzg2l-cpg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index b3a1533970e5..f626d2704477 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
mult = MDIV(val1) + KDIV(val1) / 65536;
- div = PDIV(val1) * (1 << SDIV(val2));
+ div = PDIV(val1) << SDIV(val2);

return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
}
--
2.25.1

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