Hi Pavel,

Thanks for the feedback.

Subject: Re: [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add
support for RZ/V2L SoC

Hi!

commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream.

The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.

Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to
take care of the DRP-AI clocks/resets.

Ok, so this reuse is quite interesting.

+++ b/drivers/clk/renesas/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-

mssr.o

obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
+obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o

They share the same source file, but the file will be different basen on
config options.

If you enable CONFIG_CLK_R9A07G044, you get g044 support but not g054
support.

If you enable CONFIG_CLK_R9A07G054, you get both g044 and g054 support,
you can't disable g044.

This is not true, we can disable g044 still. see rzg2l_cpg.c, there is a guard
for CONFIG_CLK_R9A07G044.

In this case,We will get unused variable warning for r9a07g044_cpg_info.

This is quite strange, but probably not a problem. For symmetry, I'd not
mind conditional compilation of g044 parts;

OK, will send patch for adding guard for r9a07g044_cpg_info.

or perhaps even better get

rid of condtional compilation of g045 parts -- I don't believe space
savings are significant.

Yes true, still it saves some bytes.

Cheers,
Biju

index 46359afef0d4..bdfabb992a20 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
+
+#ifdef CONFIG_CLK_R9A07G054
+const struct rzg2l_cpg_info r9a07g054_cpg_info = {
+ /* Core Clocks */
+ .core_clks = core_clks.common,
+ .num_core_clks = ARRAY_SIZE(core_clks.common) +

ARRAY_SIZE(core_clks.drp),

+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r9a07g044_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
+
+ /* Module Clocks */
+ .mod_clks = mod_clks.common,
+ .num_mod_clks = ARRAY_SIZE(mod_clks.common) +

ARRAY_SIZE(mod_clks.drp),

+ .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
+
+ /* Resets */
+ .resets = r9a07g044_resets,
+ .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
};
+#endif
diff --git a/drivers/clk/renesas/rzg2l-cpg.c
b/drivers/clk/renesas/rzg2l-cpg.c index edd0abe34a37..486d0656c58a
100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -952,6 +952,12 @@ static const struct of_device_id

rzg2l_cpg_match[] = {

.compatible = "renesas,r9a07g044-cpg",
.data = &r9a07g044_cpg_info,
},
+#endif
+#ifdef CONFIG_CLK_R9A07G054
+ {
+ .compatible = "renesas,r9a07g054-cpg",
+ .data = &r9a07g054_cpg_info,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/rzg2l-cpg.h
b/drivers/clk/renesas/rzg2l-cpg.h index 5729d102034b..ce657beaf160
100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -203,5 +203,6 @@ struct rzg2l_cpg_info { };

extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
+extern const struct rzg2l_cpg_info r9a07g054_cpg_info;

#endif
--
2.25.1

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