[PATCH 5.10.y-cip 02/13] arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection


Biju Das
 

commit 5c65ad12785205d5c57bd92e19d0296f93c19e33 upstream.

This patch replaces EMMC/SDHI macros with SW_SD0_DEV_SEL DIP-Switch
macro for eMMC/SDHI device selection.

Signed-off-by: Biju Das <biju.das.jz@...>
Link: https://lore.kernel.org/r/20220204143132.3608-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 14 ++------------
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 2 ++
2 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 6ebda3724f2c..90cb7ec45751 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -8,16 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

-/* SW1[2] should be at OFF position to enable 64 GB eMMC */
-#define EMMC 1
-
-/*
- * To enable uSD card on CN3,
- * SW1[2] should be at ON position.
- * Disable eMMC by setting "#define EMMC 0" above.
- */
-#define SDHI (!EMMC)
-
/ {
aliases {
ethernet0 = &eth0;
@@ -185,7 +175,7 @@ sd0_mux_uhs {
};
};

-#if SDHI
+#if (!SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -200,7 +190,7 @@ &sdhi0 {
};
#endif

-#if EMMC
+#if SW_SD0_DEV_SEL
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 28f21c287ba3..df7631fe5fac 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -18,6 +18,8 @@
* Please change below macros according to SW1 setting
*/

+#define SW_SD0_DEV_SEL 1
+
#define SW_SCIF_CAN 0
#if (SW_SCIF_CAN)
/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
--
2.25.1

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