Re: [PATCH 5.10.y-cip] clk: renesas: rzg2l: Fix reset status function


Pavel Machek
 

Hi!

commit 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 upstream.

As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
reset signal is not applied (deassert state) and 1 means reset signal
is applied (assert state).

reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.

This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.
Looks ok to me. I can apply it if it passes testing and there are no
other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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