- Preparing isar-cip-core for RZ/Five
Re: Preparing isar-cip-core for RZ/Five
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From: Jan Kiszka <jan.kiszka@...>
Sent: 06 October 2022 07:50
To: Pavel Machek <pavel@...>; Chris Paterson
<Chris.Paterson2@...>; Prabhakar Mahadev Lad
<prabhakar.mahadev-lad.rj@...>; Hung Tran
Cc: cip-dev <cip-dev@...>
Subject: Re: Preparing isar-cip-core for RZ/Five
On 06.10.22 08:29, Jan Kiszka wrote:
On 05.10.22 20:21, Pavel Machek wrote:rather
But due to the weird U-Boot setup, I had to add some hacks,
than a proper boot process.
Test by flashing the image to an SD-Card switching to SD booting
Maybe we can find a better solution for the boot procedure before
moving forward with this.
Anyway, now we have a real distribution on this board. Pavel, can
you re-check what you observed, if those issues persist with
Hmm, seems the issue persists:
I believe I was running Debian; two versions and Ubuntu, IIRC :-).
Can you check if ldconfig and gcc work for you? That were the
roadblocks I was hitting. If they do, I'll be interested in details
of your setup.
[ 297.146728] ldconfig: unhandled signal 4 code 0x1 at
0x00000000000380c8 in ldconfig[10000+83000] [ 297.146768] CPU: 0
497 Comm: ldconfig Not tainted 5.10.83-cip1-riscv-renesas #1 [of
297.146775] epc: 00000000000380c8 ra : 0000000000015382 sp :
0000003fffe01c10 [ 297.146782] gp : 0000000000099da8 tp :
0000003fda772800 t0 : 0000003fda7787c0 [ 297.146788] t1 :
0000003fda8065a8 t2 : 0000002acbbda7a0 s0 : 0000002afa2ec890 [
297.146794] s1 : 0000000000000001 a0 : 0000003fffe01d18 a1 :
0000000000000001 [ 297.146800] a2 : 0000003fffe01c88 a3 :
0000000000000000 a4 : 0000003fffe01d18 [ 297.146806] a5 :
000000000009736e a6 : 0000003fffe01c80 a7 : 00000000000000dd [
297.146812] s2 : 0000003fffe01c88 s3 : 0000000000000000 s4 :
0000000000000000 [ 297.146819] s5 : 00000000000105a4 s6 :
000000000009e670 s7 : 0000002afa2ec850 [ 297.146824] s8 :
0000002afa2ec710 s9 : 0000000000000000 s10: 0000002acbbe39c8 [
297.146830] s11: 0000002acbbe3938 t3 : 0000002acbaf2610 t4 :
00000000000925a8 [ 297.146835] t5 : 0000000000000004 t6 :
0000000000000000 [ 297.146842] status: 0000000200004020 badaddr:
00000000a01253cf cause: 0000000000000002
(gdb) disassemble $pc,+0x10
Dump of assembler code from 0x380c8 to 0x380d8:
=> 0x00000000000380c8: auipc a2,0x66
0x00000000000380cc: addi a2,a2,2000 # 0x9e898
0x00000000000380d0: sd a0,0(a2)
0x00000000000380d2: mv a5,sp
0x00000000000380d4: addi a4,sp,416
0x00000000000380d6: sd zero,0(a5)
End of assembler dump.
Do we have any instruction set restrictions that prevents the usage
distros on this CPU? Under QEMU, we come along here as well andauipc was introduced with ISA 2.0, around 2019 - please don't tell me
execute this without problems. Some infamous Intel CPU comes to my
mind at this point - hope, history does not repeat here....
we are on 1.0 here.
I have seen similar issue with yocto dunfell release, If I go higher up to kirkstone release I see there is patch
add-riscv-support.patch  (I haven't tried this release yet though).
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