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[PATCH 6/9] clk: renesas: rcar-gen3: Add support for mode pin clock selection

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Make the existing support for selecting between clean and SSCG clocks
using MD12 more generic, to allow using other mode pins for arbitrary
clock selection.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
(cherry picked from commit cd51e427e050f6a3d3bc3e0e38ad30974a52cb44)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 10 ++++------
drivers/clk/renesas/rcar-gen3-cpg.h | 13 +++++++++----
2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 19a7782..4346fde 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -539,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
parent = clks[cpg_clk_extalr];
break;

- case CLK_TYPE_GEN3_PE:
+ case CLK_TYPE_GEN3_MDSEL:
/*
- * Peripheral clock with a fixed divider, selectable between
- * clean and spread spectrum parents using MD12
+ * Clock selectable between two parents and two fixed dividers
+ * using a mode pin
*/
- if (cpg_mode & BIT(12)) {
- /* Clean */
+ if (cpg_mode & BIT(core->offset)) {
div = core->div & 0xffff;
} else {
- /* SCCG */
parent = clks[core->parent >> 16];
if (IS_ERR(parent))
return ERR_CAST(parent);
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 7c49aeb..04dc45d 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -20,7 +20,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL4,
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_R,
- CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
@@ -30,11 +30,16 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)

+#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
+ (_parent0) << 16 | (_parent1), \
+ .div = (_div0) << 16 | (_div1), .offset = _md)
+
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
_div_clean) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
- (_parent_sscg) << 16 | (_parent_clean), \
- .div = (_div_sscg) << 16 | (_div_clean))
+ DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
+ _parent_clean, _div_clean)
+
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)

--
2.7.4


[PATCH 5/9] clk: renesas: rcar-gen3: Add support for RCKSEL clock selection

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Add a clock type and macro for defining clocks where the parent and
divider are selected based on the value of the RCKCR.CKSEL bit.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
(cherry picked from commit b9d0b84b3db8552f033d5051393b90852b977a76)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 23 ++++++++++++++++++++---
drivers/clk/renesas/rcar-gen3-cpg.h | 7 ++++++-
2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 7533a51..19a7782 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -1,7 +1,7 @@
/*
* R-Car Gen3 Clock Pulse Generator
*
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
*
* Based on clk-rcar-gen3.c
*
@@ -31,6 +31,8 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4

+#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
+
struct cpg_simple_notifier {
struct notifier_block nb;
void __iomem *reg;
@@ -444,7 +446,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
unsigned int div = 1;
u32 value;

- parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
+ parent = clks[core->parent & 0xffff]; /* some types use high bits */
if (IS_ERR(parent))
return ERR_CAST(parent);

@@ -524,7 +526,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,

if (clk_get_rate(clks[cpg_clk_extalr])) {
parent = clks[cpg_clk_extalr];
- value |= BIT(15);
+ value |= CPG_RCKCR_CKSEL;
}

writel(value, csn->reg);
@@ -570,6 +572,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
div = cpg_pll_config->osc_prediv * core->div;
break;

+ case CLK_TYPE_GEN3_RCKSEL:
+ /*
+ * Clock selectable between two parents and two fixed dividers
+ * using RCKCR.CKSEL
+ */
+ if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
+ div = core->div & 0xffff;
+ } else {
+ parent = clks[core->parent >> 16];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+ div = core->div >> 16;
+ }
+ break;
+
default:
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index d7d84d9..7c49aeb 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -1,7 +1,7 @@
/*
* R-Car Gen3 Clock Pulse Generator
*
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
+ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
};

#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
@@ -37,6 +38,10 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)

+#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
+ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
+
struct rcar_gen3_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
--
2.7.4


[PATCH 4/9] clk: renesas: cpg-mssr: Add support for fixed rate clocks

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Add support for defining fixed rate clocks, to be used for on-chip
oscillators.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 0d2602d750152f9fcf3d9af9466f3d67b60aa646)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/clk/renesas/renesas-cpg-mssr.c | 5 +++++
drivers/clk/renesas/renesas-cpg-mssr.h | 3 +++
2 files changed, 8 insertions(+)

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index f4b013e..e043389 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
}
break;

+ case CLK_TYPE_FR:
+ clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
+ core->mult);
+ break;
+
default:
if (info->cpg_clk_register)
clk = info->cpg_clk_register(dev, core, info,
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 642f720..87bb8f3 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -38,6 +38,7 @@ enum clk_types {
CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
+ CLK_TYPE_FR, /* Fixed Rate Clock */

/* Custom definitions start here */
CLK_TYPE_CUSTOM,
@@ -56,6 +57,8 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
+#define DEF_RATE(_name, _id, _rate) \
+ DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)

/*
* Definitions of Module Clocks
--
2.7.4


[PATCH 3/9] clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider

Biju Das <biju.das@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.

On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and
thus must be specified in the configuration structure.

Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@...>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 38c79e2899a66096583f3377c64b35f30584f1b4)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 7 +++++++
drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++
2 files changed, 11 insertions(+)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 628b63b..7533a51 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -563,6 +563,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
return cpg_z_clk_register(core->name, __clk_get_name(parent),
base, CPG_FRQCRC_Z2FC_MASK);

+ case CLK_TYPE_GEN3_OSC:
+ /*
+ * Clock combining OSC EXTAL predivider and a fixed divider
+ */
+ div = cpg_pll_config->osc_prediv * core->div;
+ break;
+
default:
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index ea4f8fc..d7d84d9 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -23,6 +23,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PE,
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
+ CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
};

#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
@@ -33,6 +34,8 @@ enum rcar_gen3_clk_types {
DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
(_parent_sscg) << 16 | (_parent_clean), \
.div = (_div_sscg) << 16 | (_div_clean))
+#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)

struct rcar_gen3_cpg_pll_config {
u8 extal_div;
@@ -40,6 +43,7 @@ struct rcar_gen3_cpg_pll_config {
u8 pll1_div;
u8 pll3_mult;
u8 pll3_div;
+ u8 osc_prediv;
};

#define CPG_RCKCR 0x240
--
2.7.4


[PATCH 2/9] clk: renesas: Add r8a774a1 CPG Core Clock Definitions

Biju Das <biju.das@...>
 

Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Fabrizio Castro <fabrizio.castro@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
(cherry picked from commit 62f32dde334302d7ebb2b3c150f404a61cfcf55e)
Signed-off-by: Biju Das <biju.das@...>
---
include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 58 +++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
new file mode 100644
index 0000000..9bc5d45
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774a1 CPG Core Clocks */
+#define R8A774A1_CLK_Z 0
+#define R8A774A1_CLK_Z2 1
+#define R8A774A1_CLK_ZG 2
+#define R8A774A1_CLK_ZTR 3
+#define R8A774A1_CLK_ZTRD2 4
+#define R8A774A1_CLK_ZT 5
+#define R8A774A1_CLK_ZX 6
+#define R8A774A1_CLK_S0D1 7
+#define R8A774A1_CLK_S0D2 8
+#define R8A774A1_CLK_S0D3 9
+#define R8A774A1_CLK_S0D4 10
+#define R8A774A1_CLK_S0D6 11
+#define R8A774A1_CLK_S0D8 12
+#define R8A774A1_CLK_S0D12 13
+#define R8A774A1_CLK_S1D2 14
+#define R8A774A1_CLK_S1D4 15
+#define R8A774A1_CLK_S2D1 16
+#define R8A774A1_CLK_S2D2 17
+#define R8A774A1_CLK_S2D4 18
+#define R8A774A1_CLK_S3D1 19
+#define R8A774A1_CLK_S3D2 20
+#define R8A774A1_CLK_S3D4 21
+#define R8A774A1_CLK_LB 22
+#define R8A774A1_CLK_CL 23
+#define R8A774A1_CLK_ZB3 24
+#define R8A774A1_CLK_ZB3D2 25
+#define R8A774A1_CLK_ZB3D4 26
+#define R8A774A1_CLK_CR 27
+#define R8A774A1_CLK_CRD2 28
+#define R8A774A1_CLK_SD0H 29
+#define R8A774A1_CLK_SD0 30
+#define R8A774A1_CLK_SD1H 31
+#define R8A774A1_CLK_SD1 32
+#define R8A774A1_CLK_SD2H 33
+#define R8A774A1_CLK_SD2 34
+#define R8A774A1_CLK_SD3H 35
+#define R8A774A1_CLK_SD3 36
+#define R8A774A1_CLK_RPC 37
+#define R8A774A1_CLK_RPCD2 38
+#define R8A774A1_CLK_MSO 39
+#define R8A774A1_CLK_HDMI 40
+#define R8A774A1_CLK_CSI0 41
+#define R8A774A1_CLK_CP 42
+#define R8A774A1_CLK_CPEX 43
+#define R8A774A1_CLK_R 44
+#define R8A774A1_CLK_OSC 45
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
--
2.7.4


[PATCH 1/9] clk: renesas: Add r8a774c0 CPG Core Clock Definitions

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
Clock Outputs, as listed in Table 8.2g ("List of Clocks
[RZ/G2E]") of the RZ/G2 Hardware User's Manual.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Reviewed-by: Rob Herring <robh@...>
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
(cherry picked from commit 0acb6b53df36b8453be4fc2563e37e84450eed25)
Signed-off-by: Biju Das <biju.das@...>
---
include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 60 +++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a774c0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
new file mode 100644
index 0000000..8fe51b6
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774c0 CPG Core Clocks */
+#define R8A774C0_CLK_Z2 0
+#define R8A774C0_CLK_ZG 1
+#define R8A774C0_CLK_ZTR 2
+#define R8A774C0_CLK_ZT 3
+#define R8A774C0_CLK_ZX 4
+#define R8A774C0_CLK_S0D1 5
+#define R8A774C0_CLK_S0D3 6
+#define R8A774C0_CLK_S0D6 7
+#define R8A774C0_CLK_S0D12 8
+#define R8A774C0_CLK_S0D24 9
+#define R8A774C0_CLK_S1D1 10
+#define R8A774C0_CLK_S1D2 11
+#define R8A774C0_CLK_S1D4 12
+#define R8A774C0_CLK_S2D1 13
+#define R8A774C0_CLK_S2D2 14
+#define R8A774C0_CLK_S2D4 15
+#define R8A774C0_CLK_S3D1 16
+#define R8A774C0_CLK_S3D2 17
+#define R8A774C0_CLK_S3D4 18
+#define R8A774C0_CLK_S0D6C 19
+#define R8A774C0_CLK_S3D1C 20
+#define R8A774C0_CLK_S3D2C 21
+#define R8A774C0_CLK_S3D4C 22
+#define R8A774C0_CLK_LB 23
+#define R8A774C0_CLK_CL 24
+#define R8A774C0_CLK_ZB3 25
+#define R8A774C0_CLK_ZB3D2 26
+#define R8A774C0_CLK_CR 27
+#define R8A774C0_CLK_CRD2 28
+#define R8A774C0_CLK_SD0H 29
+#define R8A774C0_CLK_SD0 30
+#define R8A774C0_CLK_SD1H 31
+#define R8A774C0_CLK_SD1 32
+#define R8A774C0_CLK_SD3H 33
+#define R8A774C0_CLK_SD3 34
+#define R8A774C0_CLK_RPC 35
+#define R8A774C0_CLK_RPCD2 36
+#define R8A774C0_CLK_ZA2 37
+#define R8A774C0_CLK_ZA8 38
+#define R8A774C0_CLK_Z2D 39
+#define R8A774C0_CLK_MSO 40
+#define R8A774C0_CLK_R 41
+#define R8A774C0_CLK_OSC 42
+#define R8A774C0_CLK_LV0 43
+#define R8A774C0_CLK_LV1 44
+#define R8A774C0_CLK_CSI0 45
+#define R8A774C0_CLK_CP 46
+#define R8A774C0_CLK_CPEX 47
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
--
2.7.4


[PATCH 0/9] Add RZ/G2[ME] Clock support

Biju Das <biju.das@...>
 

This patch series aims to add Clock support for RZ/G2[ME] SoCs.

This patch series is based on linux-4.19.y-cip and all the patches
in this series are cherry-picked from linux rc tree.

This patch series is depend on the below patch series
https://patchwork.kernel.org/project/cip-dev/list/?series=94893

Biju Das (2):
clk: renesas: Add r8a774a1 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add r8a774a1 support

Fabrizio Castro (3):
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
clk: renesas: cpg-mssr: Add r8a774c0 support

Geert Uytterhoeven (4):
clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
clk: renesas: cpg-mssr: Add support for fixed rate clocks
clk: renesas: rcar-gen3: Add support for RCKSEL clock selection
clk: renesas: rcar-gen3: Add support for mode pin clock selection

.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 +-
drivers/clk/renesas/Kconfig | 10 +
drivers/clk/renesas/Makefile | 2 +
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 323 +++++++++++++++++++++
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 286 ++++++++++++++++++
drivers/clk/renesas/rcar-gen3-cpg.c | 40 ++-
drivers/clk/renesas/rcar-gen3-cpg.h | 24 +-
drivers/clk/renesas/renesas-cpg-mssr.c | 17 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 5 +
include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 58 ++++
include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 60 ++++
11 files changed, 817 insertions(+), 18 deletions(-)
create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c
create mode 100644 drivers/clk/renesas/r8a774c0-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h
create mode 100644 include/dt-bindings/clock/r8a774c0-cpg-mssr.h

--
2.7.4


[PATCH 18/18] soc: renesas: rcar-rst: Add support for RZ/G2E

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 91e95ecd4b4ff35624ac48bdf6dcf2d855f0b63e)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/soc/renesas/Kconfig | 6 +++---
drivers/soc/renesas/rcar-rst.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 163e666..614d767 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,9 +3,9 @@ config SOC_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
- ARCH_R8A774A1 || ARCH_R8A7795 || ARCH_R8A7796 || \
- ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \
- ARCH_R8A77990 || ARCH_R8A77995
+ ARCH_R8A774A1 || ARCH_R8A774C0 || ARCH_R8A7795 || \
+ ARCH_R8A7796 || ARCH_R8A77965 || ARCH_R8A77970 || \
+ ARCH_R8A77980 || ARCH_R8A77990 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index a447873..d5e31f4 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -47,6 +47,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
/* RZ/G2 is handled like R-Car Gen3 */
{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
+ { .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen1 */
{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
--
2.7.4


[PATCH 17/18] dt-bindings: reset: rcar-rst: Document r8a774c0 rst

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Document bindings for the RZ/G2E (a.k.a. R8A774C0) reset
module.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Acked-by: Philipp Zabel <p.zabel@...>
Reviewed-by: Rob Herring <robh@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit fe46b8229f287e912b8c8d28bf8dde4cd704c17e)
Signed-off-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index e4fe0ab..25e6db5 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -19,6 +19,7 @@ Required properties:
- "renesas,r8a7745-rst" (RZ/G1E)
- "renesas,r8a77470-rst" (RZ/G1C)
- "renesas,r8a774a1-rst" (RZ/G2M)
+ - "renesas,r8a774c0-rst" (RZ/G2E)
- "renesas,r8a7778-reset-wdt" (R-Car M1A)
- "renesas,r8a7779-reset-wdt" (R-Car H1)
- "renesas,r8a7790-rst" (R-Car H2)
--
2.7.4


[PATCH 16/18] soc: renesas: rcar-rst: Add support for RZ/G2M

Biju Das <biju.das@...>
 

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 3116d859e7b15d3740afd44c975cdb34a4c1246e)
Signed-off-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
drivers/soc/renesas/Kconfig | 6 +++---
drivers/soc/renesas/rcar-rst.c | 4 +++-
3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
index 67e83b0..e4fe0ab 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -18,6 +18,7 @@ Required properties:
- "renesas,r8a7743-rst" (RZ/G1M)
- "renesas,r8a7745-rst" (RZ/G1E)
- "renesas,r8a77470-rst" (RZ/G1C)
+ - "renesas,r8a774a1-rst" (RZ/G2M)
- "renesas,r8a7778-reset-wdt" (R-Car M1A)
- "renesas,r8a7779-reset-wdt" (R-Car H1)
- "renesas,r8a7790-rst" (R-Car H2)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index e50e77c..163e666 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,9 +3,9 @@ config SOC_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
- ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \
- ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \
- ARCH_R8A77995
+ ARCH_R8A774A1 || ARCH_R8A7795 || ARCH_R8A7796 || \
+ ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \
+ ARCH_R8A77990 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index d9c1034..a447873 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -41,10 +41,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
};

static const struct of_device_id rcar_rst_matches[] __initconst = {
- /* RZ/G is handled like R-Car Gen2 */
+ /* RZ/G1 is handled like R-Car Gen2 */
{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
+ /* RZ/G2 is handled like R-Car Gen3 */
+ { .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen1 */
{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
--
2.7.4


[PATCH 15/18] soc: renesas: r8a774c0-sysc: Fix initialization order of 3DG-{A, B}

Biju Das <biju.das@...>
 

The workaround for the wrong hierarchy of the 3DG-{A,B} power domains on
RZ/G2E ES1.0 corrected the parent domains. However, the 3DG-{A,B} power
domains were still initialized and powered in the wrong order, causing
3DG operation to fail.

Fix this by changing the order in the table at runtime, when running on
an affected SoC.

This work is based on the work done by Geert for R-Car E3.

Fixes: f37d211c687588328 ("soc: renesas: rcar-sysc: Add r8a774c0 support")

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit a64597227d0de5610407fcc95dc835745a53f5d0)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/soc/renesas/r8a774c0-sysc.c | 23 ++++-------------------
1 file changed, 4 insertions(+), 19 deletions(-)

diff --git a/drivers/soc/renesas/r8a774c0-sysc.c b/drivers/soc/renesas/r8a774c0-sysc.c
index e1ac4c0..11050e1 100644
--- a/drivers/soc/renesas/r8a774c0-sysc.c
+++ b/drivers/soc/renesas/r8a774c0-sysc.c
@@ -28,19 +28,6 @@ static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
{ "3dg-b", 0x100, 1, R8A774C0_PD_3DG_B, R8A774C0_PD_3DG_A },
};

-static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
- unsigned int num_areas, u8 id,
- int new_parent)
-{
- unsigned int i;
-
- for (i = 0; i < num_areas; i++)
- if (areas[i].isr_bit == id) {
- areas[i].parent = new_parent;
- return;
- }
-}
-
/* Fixups for RZ/G2E ES1.0 revision */
static const struct soc_device_attribute r8a774c0[] __initconst = {
{ .soc_id = "r8a774c0", .revision = "ES1.0" },
@@ -50,12 +37,10 @@ static const struct soc_device_attribute r8a774c0[] __initconst = {
static int __init r8a774c0_sysc_init(void)
{
if (soc_device_match(r8a774c0)) {
- rcar_sysc_fix_parent(r8a774c0_areas,
- ARRAY_SIZE(r8a774c0_areas),
- R8A774C0_PD_3DG_A, R8A774C0_PD_3DG_B);
- rcar_sysc_fix_parent(r8a774c0_areas,
- ARRAY_SIZE(r8a774c0_areas),
- R8A774C0_PD_3DG_B, R8A774C0_PD_ALWAYS_ON);
+ /* Fix incorrect 3DG hierarchy */
+ swap(r8a774c0_areas[6], r8a774c0_areas[7]);
+ r8a774c0_areas[6].parent = R8A774C0_PD_ALWAYS_ON;
+ r8a774c0_areas[7].parent = R8A774C0_PD_3DG_B;
}

return 0;
--
2.7.4


[PATCH 14/18] soc: renesas: rcar-sysc: Add r8a774c0 support

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Add support for the RZ/G2E (R8A774C0) SoC power areas to the
R-Car SYSC driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit f37d211c687588328c083f4523c4a26620dc5bb6)
Signed-off-by: Biju Das <biju.das@...>
---
drivers/soc/renesas/Kconfig | 5 +++
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a774c0-sysc.c | 68 +++++++++++++++++++++++++++++++++++++
drivers/soc/renesas/rcar-sysc.c | 3 ++
drivers/soc/renesas/rcar-sysc.h | 1 +
5 files changed, 78 insertions(+)
create mode 100644 drivers/soc/renesas/r8a774c0-sysc.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index d769330..e50e77c 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -10,6 +10,7 @@ config SOC_RENESAS
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
select SYSC_R8A774A1 if ARCH_R8A774A1
+ select SYSC_R8A774C0 if ARCH_R8A774C0
select SYSC_R8A7779 if ARCH_R8A7779
select SYSC_R8A7790 if ARCH_R8A7790
select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
@@ -42,6 +43,10 @@ config SYSC_R8A774A1
bool "RZ/G2M System Controller support" if COMPILE_TEST
select SYSC_RCAR

+config SYSC_R8A774C0
+ bool "RZ/G2E System Controller support" if COMPILE_TEST
+ select SYSC_RCAR
+
config SYSC_R8A7779
bool "R-Car H1 System Controller support" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 6adb9d6..3bdd7db 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
+obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o
obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o
obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o
diff --git a/drivers/soc/renesas/r8a774c0-sysc.c b/drivers/soc/renesas/r8a774c0-sysc.c
new file mode 100644
index 0000000..e1ac4c0
--- /dev/null
+++ b/drivers/soc/renesas/r8a774c0-sysc.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2E System Controller
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car E3 System Controller
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/sys_soc.h>
+
+#include <dt-bindings/power/r8a774c0-sysc.h>
+
+#include "rcar-sysc.h"
+
+static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
+ { "always-on", 0, 0, R8A774C0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ { "ca53-scu", 0x140, 0, R8A774C0_PD_CA53_SCU, R8A774C0_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca53-cpu0", 0x200, 0, R8A774C0_PD_CA53_CPU0, R8A774C0_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu1", 0x200, 1, R8A774C0_PD_CA53_CPU1, R8A774C0_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "a3vc", 0x380, 0, R8A774C0_PD_A3VC, R8A774C0_PD_ALWAYS_ON },
+ { "a2vc1", 0x3c0, 1, R8A774C0_PD_A2VC1, R8A774C0_PD_A3VC },
+ { "3dg-a", 0x100, 0, R8A774C0_PD_3DG_A, R8A774C0_PD_ALWAYS_ON },
+ { "3dg-b", 0x100, 1, R8A774C0_PD_3DG_B, R8A774C0_PD_3DG_A },
+};
+
+static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
+ unsigned int num_areas, u8 id,
+ int new_parent)
+{
+ unsigned int i;
+
+ for (i = 0; i < num_areas; i++)
+ if (areas[i].isr_bit == id) {
+ areas[i].parent = new_parent;
+ return;
+ }
+}
+
+/* Fixups for RZ/G2E ES1.0 revision */
+static const struct soc_device_attribute r8a774c0[] __initconst = {
+ { .soc_id = "r8a774c0", .revision = "ES1.0" },
+ { /* sentinel */ }
+};
+
+static int __init r8a774c0_sysc_init(void)
+{
+ if (soc_device_match(r8a774c0)) {
+ rcar_sysc_fix_parent(r8a774c0_areas,
+ ARRAY_SIZE(r8a774c0_areas),
+ R8A774C0_PD_3DG_A, R8A774C0_PD_3DG_B);
+ rcar_sysc_fix_parent(r8a774c0_areas,
+ ARRAY_SIZE(r8a774c0_areas),
+ R8A774C0_PD_3DG_B, R8A774C0_PD_ALWAYS_ON);
+ }
+
+ return 0;
+}
+
+const struct rcar_sysc_info r8a774c0_sysc_info __initconst = {
+ .init = r8a774c0_sysc_init,
+ .areas = r8a774c0_areas,
+ .num_areas = ARRAY_SIZE(r8a774c0_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index fe32f7a..e63d7a2 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -278,6 +278,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A774A1
{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
#endif
+#ifdef CONFIG_SYSC_R8A774C0
+ { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
+#endif
#ifdef CONFIG_SYSC_R8A7779
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
#endif
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index 33defe6..dc71f49 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -53,6 +53,7 @@ extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;
extern const struct rcar_sysc_info r8a774a1_sysc_info;
+extern const struct rcar_sysc_info r8a774c0_sysc_info;
extern const struct rcar_sysc_info r8a7779_sysc_info;
extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info;
--
2.7.4


[PATCH 13/18] dt-bindings: power: rcar-sysc: Document r8a774c0 sysc

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Document bindings for the RZ/G2E (a.k.a. R8A774C0) system
controller.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 39dc9a103bc587d32a0416c5a47483a6e9ef88e2)
Signed-off-by: Biju Das <biju.das@...>
---
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index 4e3ec6a..4cb97d4 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -11,6 +11,7 @@ Required properties:
- "renesas,r8a7745-sysc" (RZ/G1E)
- "renesas,r8a77470-sysc" (RZ/G1C)
- "renesas,r8a774a1-sysc" (RZ/G2M)
+ - "renesas,r8a774c0-sysc" (RZ/G2E)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)
--
2.7.4


[PATCH 12/18] soc: renesas: rcar-sysc: Add r8a774a1 support

Biju Das <biju.das@...>
 

Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
driver.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 7f0e99cc916933ecd7fd407e2eb42448198e0404)
Signed-off-by: Biju Das <biju.das@...>
---
.../bindings/power/renesas,rcar-sysc.txt | 1 +
drivers/soc/renesas/Kconfig | 5 +++
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a774a1-sysc.c | 45 ++++++++++++++++++++++
drivers/soc/renesas/rcar-sysc.c | 3 ++
drivers/soc/renesas/rcar-sysc.h | 1 +
6 files changed, 56 insertions(+)
create mode 100644 drivers/soc/renesas/r8a774a1-sysc.c

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
index 180ae65..4e3ec6a 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,r8a7743-sysc" (RZ/G1M)
- "renesas,r8a7745-sysc" (RZ/G1E)
- "renesas,r8a77470-sysc" (RZ/G1C)
+ - "renesas,r8a774a1-sysc" (RZ/G2M)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 1d824cb..d769330 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -9,6 +9,7 @@ config SOC_RENESAS
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
+ select SYSC_R8A774A1 if ARCH_R8A774A1
select SYSC_R8A7779 if ARCH_R8A7779
select SYSC_R8A7790 if ARCH_R8A7790
select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
@@ -37,6 +38,10 @@ config SYSC_R8A77470
bool "RZ/G1C System Controller support" if COMPILE_TEST
select SYSC_RCAR

+config SYSC_R8A774A1
+ bool "RZ/G2M System Controller support" if COMPILE_TEST
+ select SYSC_RCAR
+
config SYSC_R8A7779
bool "R-Car H1 System Controller support" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index c37b080..6adb9d6 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
+obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o
obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o
diff --git a/drivers/soc/renesas/r8a774a1-sysc.c b/drivers/soc/renesas/r8a774a1-sysc.c
new file mode 100644
index 0000000..9db51ff
--- /dev/null
+++ b/drivers/soc/renesas/r8a774a1-sysc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2M System Controller
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car M3-W System Controller
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a774a1-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a774a1_areas[] __initconst = {
+ { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
+ PD_CPU_NOCR },
+ { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
+ PD_CPU_NOCR },
+ { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON },
+ { "a2vc0", 0x3c0, 0, R8A774A1_PD_A2VC0, R8A774A1_PD_A3VC },
+ { "a2vc1", 0x3c0, 1, R8A774A1_PD_A2VC1, R8A774A1_PD_A3VC },
+ { "3dg-a", 0x100, 0, R8A774A1_PD_3DG_A, R8A774A1_PD_ALWAYS_ON },
+ { "3dg-b", 0x100, 1, R8A774A1_PD_3DG_B, R8A774A1_PD_3DG_A },
+};
+
+const struct rcar_sysc_info r8a774a1_sysc_info __initconst = {
+ .areas = r8a774a1_areas,
+ .num_areas = ARRAY_SIZE(r8a774a1_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 029188e..fe32f7a 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -275,6 +275,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A77470
{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
#endif
+#ifdef CONFIG_SYSC_R8A774A1
+ { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
+#endif
#ifdef CONFIG_SYSC_R8A7779
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
#endif
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index a22e7cf..33defe6 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -52,6 +52,7 @@ struct rcar_sysc_info {
extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;
+extern const struct rcar_sysc_info r8a774a1_sysc_info;
extern const struct rcar_sysc_info r8a7779_sysc_info;
extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info;
--
2.7.4


[PATCH 11/18] dt-bindings: power: Add r8a774c0 SYSC power domain definitions

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

This patch adds power domain indices for RZ/G2E.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit cb391265bca42f17c59d90e842a6bc582e3e2211)
Signed-off-by: Biju Das <biju.das@...>
---
include/dt-bindings/power/r8a774c0-sysc.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 include/dt-bindings/power/r8a774c0-sysc.h

diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h
new file mode 100644
index 0000000..9922d4c
--- /dev/null
+++ b/include/dt-bindings/power/r8a774c0-sysc.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774C0_PD_CA53_CPU0 5
+#define R8A774C0_PD_CA53_CPU1 6
+#define R8A774C0_PD_A3VC 14
+#define R8A774C0_PD_3DG_A 17
+#define R8A774C0_PD_3DG_B 18
+#define R8A774C0_PD_CA53_SCU 21
+#define R8A774C0_PD_A2VC1 26
+
+/* Always-on power area */
+#define R8A774C0_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */
--
2.7.4


[PATCH 10/18] dt-bindings: power: Add r8a774a1 SYSC power domain definitions

Biju Das <biju.das@...>
 

This patch adds power domain indices for RZ/G2M.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 066f7e63b9ed0badffc32bcf135e59658b423999)
Signed-off-by: Biju Das <biju.das@...>
---
include/dt-bindings/power/r8a774a1-sysc.h | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h

diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h
new file mode 100644
index 0000000..580f431
--- /dev/null
+++ b/include/dt-bindings/power/r8a774a1-sysc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A1_PD_CA57_CPU0 0
+#define R8A774A1_PD_CA57_CPU1 1
+#define R8A774A1_PD_CA53_CPU0 5
+#define R8A774A1_PD_CA53_CPU1 6
+#define R8A774A1_PD_CA53_CPU2 7
+#define R8A774A1_PD_CA53_CPU3 8
+#define R8A774A1_PD_CA57_SCU 12
+#define R8A774A1_PD_A3VC 14
+#define R8A774A1_PD_3DG_A 17
+#define R8A774A1_PD_3DG_B 18
+#define R8A774A1_PD_CA53_SCU 21
+#define R8A774A1_PD_A2VC0 25
+#define R8A774A1_PD_A2VC1 26
+
+/* Always-on power area */
+#define R8A774A1_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
--
2.7.4


[PATCH 09/18] arm64: defconfig: enable R8A774C0 SoC

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Enable the Renesas RZ/G2E (R8A774C0) SoC in the ARM64 defconfig.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 76506880eac66cb1f189a993c39ad0fcba723b99)
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3f1868c..e6ec985 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -51,6 +51,7 @@ CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774C0=y
CONFIG_ARCH_R8A7795=y
CONFIG_ARCH_R8A7796=y
CONFIG_ARCH_R8A77965=y
--
2.7.4


[PATCH 08/18] arm64: defconfig: enable R8A774A1 SoC

Biju Das <biju.das@...>
 

Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64 defconfig.

Signed-off-by: Biju Das <biju.das@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 48acc8440a78596384881ba773e47d55c4de2ebc)
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index db8d364..3f1868c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -50,6 +50,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A7795=y
CONFIG_ARCH_R8A7796=y
CONFIG_ARCH_R8A77965=y
--
2.7.4


[PATCH 07/18] arm64: Add Renesas R8A774C0 support

Biju Das <biju.das@...>
 

From: Fabrizio Castro <fabrizio.castro@...>

Add configuration option for the RZ/G2E (R8A774C0) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@...>
Reviewed-by: Biju Das <biju.das@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 692dce77dfb71b5eaf896d3cdc7ef72f70631b14)
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/Kconfig.platforms | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 531ea50..71ae51d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -192,6 +192,12 @@ config ARCH_R8A774A1
help
This enables support for the Renesas RZ/G2M SoC.

+config ARCH_R8A774C0
+ bool "Renesas RZ/G2E SoC Platform"
+ depends on ARCH_RENESAS
+ help
+ This enables support for the Renesas RZ/G2E SoC.
+
config ARCH_R8A7795
bool "Renesas R-Car H3 SoC Platform"
depends on ARCH_RENESAS
--
2.7.4


[PATCH 06/18] arm64: Add Renesas R8A774A1 support

Biju Das <biju.das@...>
 

Add configuration option for the RZ/G2M (R8A774A1) SoC.

Signed-off-by: Biju Das <biju.das@...>
Reviewed-by: Chris Paterson <chris.paterson2@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Simon Horman <horms+renesas@...>
(cherry picked from commit 5afa67792d0a25d5642cd6929ed0f92b5e7f5076)
Signed-off-by: Biju Das <biju.das@...>
---
arch/arm64/Kconfig.platforms | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 393d2b5..531ea50 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -186,6 +186,12 @@ config ARCH_RENESAS
help
This enables support for the ARMv8 based Renesas SoCs.

+config ARCH_R8A774A1
+ bool "Renesas RZ/G2M SoC Platform"
+ depends on ARCH_RENESAS
+ help
+ This enables support for the Renesas RZ/G2M SoC.
+
config ARCH_R8A7795
bool "Renesas R-Car H3 SoC Platform"
depends on ARCH_RENESAS
--
2.7.4

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