Date   

Re: [PATCH 00/36] Add Hihope RZ/G2H basic board support

Pavel Machek
 

Hi!

This patch series add basic support for Hihope RZ/G2H based on
r8a774e1 SoC to 4.19.y-cip kernel. All patches in this series
are cherry-picked from mainline.
This patch series depends on [1]
[1]:
https://patchwork.kernel.org/project/cip-dev/list/?series=335409
For the record, these patches look good to me.

So we need to decide what to do with that dependency.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


[ANNOUNCE] Release v4.19.140-cip33

Nobuhiro Iwamatsu
 

Hi all,

CIP kernel team has released Linux kernel v4.19.140-cip33.
The linux-4.19.y-cip tree has been updated base version from v4.19.138
to v4.19.140, and the fix about DRM is added.

You can get this release via the git tree at:

v4.19.140-cip33:
repository:
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git
branch:
linux-4.19.y-cip
commit hash:
03cdb749e6350f0403badbf7931e420ea7514f56
added commits:
CIP: Bump version suffix to -cip33 after merge from stable
drm: atomic helper: fix W=1 warnings
drm: Add drm_atomic_get_old/new_private_obj_state
drm: of: Fix linking when CONFIG_OF is not set

Best regards,
Nobuhiro


Re: [isar-cip-core][PATCH 1/2] ci: Rewrite using extends

Jan Kiszka
 

On 21.08.20 17:04, Jan Kiszka wrote:
On 20.08.20 10:24, Nobuhiro Iwamatsu wrote:
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>
---
.gitlab-ci.yml | 70 +++++++++++++++++++++++++++++---------
scripts/deploy-cip-core.sh | 8 +++--
2 files changed, 60 insertions(+), 18 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 3fe7af2..e23345f 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,10 +2,17 @@ image: kasproject/kas-isar:1.1

variables:
GIT_STRATEGY: clone
+ release: buster
+ extention: base
+ use_rt: enable
+ targz: enable
+ dtb: none

-all:
- stage: build
- script:
+stages:
+ - build
+
+default:
+ before_script:
- export http_proxy=$HTTP_PROXY
- export https_proxy=$HTTPS_PROXY
- export ftp_proxy=$FTP_PROXY
@@ -13,20 +20,51 @@ all:
- export AWS_ACCESS_KEY_ID=$AWS_ACCESS_KEY_ID
- export AWS_SECRET_ACCESS_KEY=$AWS_SECRET_ACCESS_KEY

- - kas build kas-cip.yml:kas/board/simatic-ipc227e.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster simatic-ipc227e
-
+.build_base:
+ stage: build
+ variables:
+ base_yaml: "kas-cip.yml:kas/board/${target}.yml"
+ script:
- sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/bbb.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster bbb am335x-boneblack.dtb
+ - if [ "${use_rt}" = "enable" ]; then base_yaml="${base_yaml}:kas/opt/rt.yml"; fi;
+ - if [ "${extention}" != "base" ]; then base_yaml="${base_yaml}:kas/opt/${extention}.yml"; fi;
+ - if [ "${targz}" = "enable" ]; then base_yaml="${base_yaml}:kas/opt/targz-img.yml"; fi;
+ - kas build ${base_yaml}
+ - scripts/deploy-cip-core.sh ${release} ${target} ${extention} ${dtb}

- - sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/iwg20m.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster iwg20m r8a7743-iwg20d-q7-dbcm-ca.dtb
+# base image
+build:simatic-ipc227e-base:
+ extends:
+ - .build_base
+ variables:
+ target: simatic-ipc227e

- - sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/rzg2m.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster hihope-rzg2m renesas/r8a774a1-hihope-rzg2m-ex.dtb
+build:bbb-base:
+ extends:
+ - .build_base
+ variables:
+ target: bbb
+ dtb: am335x-boneblack.dtb

- - sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/qemu-amd64.yml:kas/opt/security.yml
+build:iwg20m-base:
+ extends:
+ - .build_base
+ variables:
+ target: iwg20m
+ dtb: r8a7743-iwg20d-q7-dbcm-ca.dtb
+
+build:hihope-rzg2m-base:
+ extends:
+ - .build_base
+ variables:
+ target: rzg2m
+ dtb: renesas/r8a774a1-hihope-rzg2m-ex.dtb
+
+build:qemu-amd64-base:
+ extends:
+ - .build_base
+ variables:
+ target: qemu-amd64
+ extention: security
+ use_rt: disable
+ targz: disable
diff --git a/scripts/deploy-cip-core.sh b/scripts/deploy-cip-core.sh
index 4c8d4c9..5b7eab9 100755
--- a/scripts/deploy-cip-core.sh
+++ b/scripts/deploy-cip-core.sh
@@ -16,9 +16,13 @@ fi

RELEASE=$1
TARGET=$2
-DTB=$3
+EXTENSION=$3
+DTB=$4

BASE_PATH=build/tmp/deploy/images/$TARGET/cip-core-image-cip-core-$RELEASE-$TARGET
+if [ "${EXTENSION}" != "base" ] ; then
+ BASE_PATH=build/tmp/deploy/images/$TARGET/cip-core-image-cip-core-$RELEASE-$TARGET-$EXTENSION
+fi

echo "Compressing cip-core-image-cip-core-$RELEASE-$TARGET.wic.img..."
xz -9 -k $BASE_PATH.wic.img
@@ -38,6 +42,6 @@ fi
aws s3 cp --no-progress $KERNEL_IMAGE s3://download.cip-project.org/cip-core/$TARGET/
aws s3 cp --no-progress $BASE_PATH-initrd.img s3://download.cip-project.org/cip-core/$TARGET/

-if [ -n "$DTB" ]; then
+if [ "$DTB" != "none" ]; then
aws s3 cp --no-progress build/tmp/work/cip-core-*/linux-cip*/*/linux-cip-*/debian/linux-image-cip*/usr/lib/linux-image-*/$DTB s3://download.cip-project.org/cip-core/$TARGET/
fi
Unfortunately, this scale out to multiple jobs seem to cause download
issues, see e.g.

- https://gitlab.com/cip-project/cip-core/isar-cip-core/-/jobs/697844276
- https://gitlab.com/cip-project/cip-core/isar-cip-core/-/jobs/696946649

First thought it was a sporadic hic-up, but it reoccurs, now with
master. Is kernel.org throttling us here?
And I'm afraid there is more broken, namely in the deployment that is
only triggered over master. Please have a look at the failing jobs.

Thanks,
Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


Re: [isar-cip-core][PATCH v4 0/6] secureboot with efibootguard

Jan Kiszka
 

On 21.08.20 11:55, Q. Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@...>

This patchset adds secureboot with efibootguard to cip-core.

The image build signs the efibootguard bootloader (bootx64.efi) and generates
a signed [unified kernel image](https://systemd.io/BOOT_LOADER_SPECIFICATION/).
A unified kernel image packs the kernel, initramfs and the kernel command-line
in one binary object. As the kernel command-line is immutable after the build
process, the previous selection of the root file system with a command-line parameter is no longer
possible. Therefore the selection of the root file-system occurs now in the initramfs.

The image uses an A/B partition layout to update the root file system. The sample implementation to
select the root file system generates a uuid and stores the id in /etc/os-release and in the initramfs.
During boot the initramfs compares its own uuid with the uuid stored in /etc/os-release of each rootfs.
If a match is found the rootfs is used for the boot.

Changes V2:

- rebase to [1]
- removed luahandler patch as it now part of [1]
- add handling for sw-description

Changes V3:

- rewrite the image id creation to ensure a new uuid is generated if a new package is
added or another change of the rootfs
- add readme section how to execute/test the software update mechnism
- adapt to version v3 of [1]
- update the patch
- add wks file for efibootguard and swupdate

[1]: a/b rootfsupdate with software update

Changes V4:

- rebase onto next 619edb509bd287277749580cbc842e57d5044756
- fix indent of ./start-qemu.sh
- whitespace fixes
- update libubootenv patch to v2
- update revision of cip-kernel-config to ca24d965adf77730caf1cd32bdfcffd69e369502
to boot secureboot with qemu
- swupdate swdescription for non-secure-boot images

Quirin Gylstorff (6):
linux-cip: Update revision of kernel config
isar-patch: Add initramfs-config patch
secure-boot: select boot partition in initramfs
secure-boot: Add secure boot with unified kernel image
secure-boot: Add Debian snakeoil keys for ease-of-use
doc: Add README for secureboot

classes/image_uuid.bbclass | 33 +++
conf/distro/debian-buster-backports.list | 1 +
conf/distro/preferences.ovmf-snakeoil.conf | 3 +
doc/README.secureboot.md | 229 ++++++++++++++++++
.../0001-u-boot-add-libubootenv.patch | 161 ++++++------
...-support-Generate-a-custom-initramfs.patch | 207 ++++++++++++++++
kas-cip.yml | 3 +
kas/opt/ebg-secure-boot-base.yml | 18 ++
kas/opt/ebg-secure-boot-snakeoil.yml | 28 +++
kas/opt/ebg-swu.yml | 4 +-
recipes-core/images/cip-core-image.bb | 12 +-
.../files/secure-boot/sw-description.tmpl | 29 +++
recipes-core/images/files/sw-description.tmpl | 19 +-
recipes-core/images/secureboot.inc | 21 ++
recipes-core/images/swupdate.inc | 21 ++
.../ebg-secure-boot-secrets_0.1.bb | 51 ++++
.../ebg-secure-boot-secrets/files/README.md | 1 +
.../files/control.tmpl | 12 +
.../files/sign_secure_image.sh.tmpl | 22 ++
.../ebg-secure-boot-snakeoil_0.1.bb | 34 +++
.../files/control.tmpl | 12 +
.../files/sign_secure_image.sh | 36 +++
.../ovmf-binaries/files/control.tmpl | 11 +
.../ovmf-binaries/ovmf-binaries_0.1.bb | 30 +++
recipes-kernel/linux/linux-cip-common.inc | 2 +-
.../files/initramfs.image_uuid.hook | 33 +++
.../files/initramfs.lsblk.hook | 29 +++
.../initramfs-config/files/postinst.ext | 3 +
.../files/secure-boot-debian-local-patch | 79 ++++++
.../initramfs-abrootfs-secureboot_0.1.bb | 38 +++
...enerate-sb-db-from-existing-certificate.sh | 16 ++
scripts/generate_secure_boot_keys.sh | 51 ++++
.../wic/plugins/source/efibootguard-boot.py | 87 ++++++-
.../wic/plugins/source/efibootguard-efi.py | 40 ++-
scripts/start-efishell.sh | 12 +
start-qemu.sh | 59 +++--
wic/ebg-signed-bootloader.inc | 2 +
wic/qemu-amd64-efibootguard-secureboot.wks | 9 +
wic/qemu-amd64-efibootguard.wks | 1 -
39 files changed, 1330 insertions(+), 129 deletions(-)
create mode 100644 classes/image_uuid.bbclass
create mode 100644 conf/distro/debian-buster-backports.list
create mode 100644 conf/distro/preferences.ovmf-snakeoil.conf
create mode 100644 doc/README.secureboot.md
create mode 100644 isar-patches/v7-0001-meta-support-Generate-a-custom-initramfs.patch
create mode 100644 kas/opt/ebg-secure-boot-base.yml
create mode 100644 kas/opt/ebg-secure-boot-snakeoil.yml
create mode 100644 recipes-core/images/files/secure-boot/sw-description.tmpl
create mode 100644 recipes-core/images/secureboot.inc
create mode 100644 recipes-core/images/swupdate.inc
create mode 100644 recipes-devtools/ebg-secure-boot-secrets/ebg-secure-boot-secrets_0.1.bb
create mode 100644 recipes-devtools/ebg-secure-boot-secrets/files/README.md
create mode 100644 recipes-devtools/ebg-secure-boot-secrets/files/control.tmpl
create mode 100644 recipes-devtools/ebg-secure-boot-secrets/files/sign_secure_image.sh.tmpl
create mode 100644 recipes-devtools/ebg-secure-boot-snakeoil/ebg-secure-boot-snakeoil_0.1.bb
create mode 100644 recipes-devtools/ebg-secure-boot-snakeoil/files/control.tmpl
create mode 100644 recipes-devtools/ebg-secure-boot-snakeoil/files/sign_secure_image.sh
create mode 100644 recipes-devtools/ovmf-binaries/files/control.tmpl
create mode 100644 recipes-devtools/ovmf-binaries/ovmf-binaries_0.1.bb
create mode 100644 recipes-support/initramfs-config/files/initramfs.image_uuid.hook
create mode 100644 recipes-support/initramfs-config/files/initramfs.lsblk.hook
create mode 100644 recipes-support/initramfs-config/files/postinst.ext
create mode 100644 recipes-support/initramfs-config/files/secure-boot-debian-local-patch
create mode 100644 recipes-support/initramfs-config/initramfs-abrootfs-secureboot_0.1.bb
create mode 100755 scripts/generate-sb-db-from-existing-certificate.sh
create mode 100755 scripts/generate_secure_boot_keys.sh
create mode 100755 scripts/start-efishell.sh
create mode 100644 wic/ebg-signed-bootloader.inc
create mode 100644 wic/qemu-amd64-efibootguard-secureboot.wks
I've taken this to next, but this also needs a hook-up with the CI system.

Thanks,
Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


[PATCH][isar-cip-core] swupdate: Add missing build dependency

Jan Kiszka
 

From: Jan Kiszka <jan.kiszka@...>

Signed-off-by: Jan Kiszka <jan.kiszka@...>
---

Quirin, please check if this is actually an unconditional dep!

classes/swupdate-config.bbclass | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/classes/swupdate-config.bbclass b/classes/swupdate-config.bbclass
index 7ce51c5..42f0654 100644
--- a/classes/swupdate-config.bbclass
+++ b/classes/swupdate-config.bbclass
@@ -15,7 +15,7 @@ inherit kconfig-snippets

BUILD_DEB_DEPENDS = " \
zlib1g-dev, debhelper, libconfig-dev, libarchive-dev, \
- python-sphinx:native, dh-systemd, libsystemd-dev"
+ python-sphinx:native, dh-systemd, libsystemd-dev, libssl-dev"

KFEATURE_lua = ""
KFEATURE_lua[BUILD_DEB_DEPENDS] = "liblua5.3-dev"
--
2.26.2

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


Re: [isar-cip-core][PATCH 1/2] ci: Rewrite using extends

Jan Kiszka
 

On 20.08.20 10:24, Nobuhiro Iwamatsu wrote:
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...>
---
.gitlab-ci.yml | 70 +++++++++++++++++++++++++++++---------
scripts/deploy-cip-core.sh | 8 +++--
2 files changed, 60 insertions(+), 18 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 3fe7af2..e23345f 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,10 +2,17 @@ image: kasproject/kas-isar:1.1

variables:
GIT_STRATEGY: clone
+ release: buster
+ extention: base
+ use_rt: enable
+ targz: enable
+ dtb: none

-all:
- stage: build
- script:
+stages:
+ - build
+
+default:
+ before_script:
- export http_proxy=$HTTP_PROXY
- export https_proxy=$HTTPS_PROXY
- export ftp_proxy=$FTP_PROXY
@@ -13,20 +20,51 @@ all:
- export AWS_ACCESS_KEY_ID=$AWS_ACCESS_KEY_ID
- export AWS_SECRET_ACCESS_KEY=$AWS_SECRET_ACCESS_KEY

- - kas build kas-cip.yml:kas/board/simatic-ipc227e.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster simatic-ipc227e
-
+.build_base:
+ stage: build
+ variables:
+ base_yaml: "kas-cip.yml:kas/board/${target}.yml"
+ script:
- sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/bbb.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster bbb am335x-boneblack.dtb
+ - if [ "${use_rt}" = "enable" ]; then base_yaml="${base_yaml}:kas/opt/rt.yml"; fi;
+ - if [ "${extention}" != "base" ]; then base_yaml="${base_yaml}:kas/opt/${extention}.yml"; fi;
+ - if [ "${targz}" = "enable" ]; then base_yaml="${base_yaml}:kas/opt/targz-img.yml"; fi;
+ - kas build ${base_yaml}
+ - scripts/deploy-cip-core.sh ${release} ${target} ${extention} ${dtb}

- - sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/iwg20m.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster iwg20m r8a7743-iwg20d-q7-dbcm-ca.dtb
+# base image
+build:simatic-ipc227e-base:
+ extends:
+ - .build_base
+ variables:
+ target: simatic-ipc227e

- - sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/rzg2m.yml:kas/opt/rt.yml:kas/opt/targz-img.yml
- - scripts/deploy-cip-core.sh buster hihope-rzg2m renesas/r8a774a1-hihope-rzg2m-ex.dtb
+build:bbb-base:
+ extends:
+ - .build_base
+ variables:
+ target: bbb
+ dtb: am335x-boneblack.dtb

- - sudo rm -rf build/tmp
- - kas build kas-cip.yml:kas/board/qemu-amd64.yml:kas/opt/security.yml
+build:iwg20m-base:
+ extends:
+ - .build_base
+ variables:
+ target: iwg20m
+ dtb: r8a7743-iwg20d-q7-dbcm-ca.dtb
+
+build:hihope-rzg2m-base:
+ extends:
+ - .build_base
+ variables:
+ target: rzg2m
+ dtb: renesas/r8a774a1-hihope-rzg2m-ex.dtb
+
+build:qemu-amd64-base:
+ extends:
+ - .build_base
+ variables:
+ target: qemu-amd64
+ extention: security
+ use_rt: disable
+ targz: disable
diff --git a/scripts/deploy-cip-core.sh b/scripts/deploy-cip-core.sh
index 4c8d4c9..5b7eab9 100755
--- a/scripts/deploy-cip-core.sh
+++ b/scripts/deploy-cip-core.sh
@@ -16,9 +16,13 @@ fi

RELEASE=$1
TARGET=$2
-DTB=$3
+EXTENSION=$3
+DTB=$4

BASE_PATH=build/tmp/deploy/images/$TARGET/cip-core-image-cip-core-$RELEASE-$TARGET
+if [ "${EXTENSION}" != "base" ] ; then
+ BASE_PATH=build/tmp/deploy/images/$TARGET/cip-core-image-cip-core-$RELEASE-$TARGET-$EXTENSION
+fi

echo "Compressing cip-core-image-cip-core-$RELEASE-$TARGET.wic.img..."
xz -9 -k $BASE_PATH.wic.img
@@ -38,6 +42,6 @@ fi
aws s3 cp --no-progress $KERNEL_IMAGE s3://download.cip-project.org/cip-core/$TARGET/
aws s3 cp --no-progress $BASE_PATH-initrd.img s3://download.cip-project.org/cip-core/$TARGET/

-if [ -n "$DTB" ]; then
+if [ "$DTB" != "none" ]; then
aws s3 cp --no-progress build/tmp/work/cip-core-*/linux-cip*/*/linux-cip-*/debian/linux-image-cip*/usr/lib/linux-image-*/$DTB s3://download.cip-project.org/cip-core/$TARGET/
fi
Unfortunately, this scale out to multiple jobs seem to cause download
issues, see e.g.

- https://gitlab.com/cip-project/cip-core/isar-cip-core/-/jobs/697844276
- https://gitlab.com/cip-project/cip-core/isar-cip-core/-/jobs/696946649

First thought it was a sporadic hic-up, but it reoccurs, now with
master. Is kernel.org throttling us here?

Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


Re: [isar-cip-core][PATCH v4 2/6] isar-patch: Add initramfs-config patch

Jan Kiszka
 

On 21.08.20 11:55, Q. Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@...>

Adapt the initramfs generation to set for example the root device
in the initramfs

Signed-off-by: Quirin Gylstorff <quirin.gylstorff@...>
---
.../0001-u-boot-add-libubootenv.patch | 161 +++++++-------
The upstream patch still has several style issues that are now reported
on every build start. Could you fix them for a new upstream version? Not
critical here, we will get the proper one once Isar merged and we updated.

Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


Re: [isar-cip-core][PATCH v4 3/6] secure-boot: select boot partition in initramfs

Jan Kiszka
 

On 21.08.20 11:55, Q. Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@...>

As the usage of a unified kernel image freeze the kernel commmandline
during build time the rootfs selection for swupdate can no longer be
done with the kernel commandline and must be done later in the boot
process. Read the root filesystem /etc/os-release and check if it contains
the same uuid as stored in the initramfs . If the uuids are the same
boot the root file system.

Signed-off-by: Quirin Gylstorff <quirin.gylstorff@...>
---
classes/image_uuid.bbclass | 33 ++++++++
.../files/initramfs.image_uuid.hook | 33 ++++++++
.../files/initramfs.lsblk.hook | 29 +++++++
.../initramfs-config/files/postinst.ext | 3 +
.../initramfs-config/files/postinst.tmpl | 31 ++++++++
.../files/secure-boot-debian-local-patch | 79 +++++++++++++++++++
.../initramfs-abrootfs-secureboot_0.1.bb | 38 +++++++++
7 files changed, 246 insertions(+)
create mode 100644 classes/image_uuid.bbclass
create mode 100644 recipes-support/initramfs-config/files/initramfs.image_uuid.hook
create mode 100644 recipes-support/initramfs-config/files/initramfs.lsblk.hook
create mode 100644 recipes-support/initramfs-config/files/postinst.ext
create mode 100644 recipes-support/initramfs-config/files/postinst.tmpl
create mode 100644 recipes-support/initramfs-config/files/secure-boot-debian-local-patch
create mode 100644 recipes-support/initramfs-config/initramfs-abrootfs-secureboot_0.1.bb

diff --git a/classes/image_uuid.bbclass b/classes/image_uuid.bbclass
new file mode 100644
index 0000000..d5337b8
--- /dev/null
+++ b/classes/image_uuid.bbclass
@@ -0,0 +1,33 @@
+#
+# CIP Core, generic profile
+#
+# Copyright (c) Siemens AG, 2020
+#
+# Authors:
+# Quirin Gylstorff <quirin.gylstorff@...>
+#
+# SPDX-License-Identifier: MIT
+#
+
+def generate_image_uuid(d):
+ import uuid
+
+ base_hash = d.getVar("BB_BASEHASH_task-do_rootfs_install", True)
+ if base_hash is None:
+ return None
+ return str(uuid.UUID(base_hash[:32], version=4))
+
+IMAGE_UUID ?= "${@generate_image_uuid(d)}"
+
+do_generate_image_uuid[vardeps] += "IMAGE_UUID"
+do_generate_image_uuid[depends] = "buildchroot-target:do_build"
+do_generate_image_uuid() {
+ sudo sed -i '/^IMAGE_UUID=.*/d' '${IMAGE_ROOTFS}/etc/os-release'
+ echo "IMAGE_UUID=\"${IMAGE_UUID}\"" | \
+ sudo tee -a '${IMAGE_ROOTFS}/etc/os-release'
+ image_do_mounts
+
+ # update initramfs to add uuid
+ sudo chroot '${IMAGE_ROOTFS}' update-initramfs -u
+}
+addtask generate_image_uuid before do_copy_boot_files after do_rootfs_install
diff --git a/recipes-support/initramfs-config/files/initramfs.image_uuid.hook b/recipes-support/initramfs-config/files/initramfs.image_uuid.hook
new file mode 100644
index 0000000..910ce84
--- /dev/null
+++ b/recipes-support/initramfs-config/files/initramfs.image_uuid.hook
@@ -0,0 +1,33 @@
+# This software is a part of ISAR.
+# Copyright (C) Siemens AG, 2020
+#
+# SPDX-License-Identifier: MIT
+
+#!/bin/sh
+set -x
+PREREQ=""
+
+prereqs()
+{
+ echo "$PREREQ"
+}
+
+case $1 in
+prereqs)
+ prereqs
+ exit 0
+ ;;
+esac
+
+. /usr/share/initramfs-tools/scripts/functions
+. /usr/share/initramfs-tools/hook-functions
+
+if [ ! -e /etc/os-release ]; then
+ echo "Warning: couldn't find /etc/os-release!"
+ exit 0
+fi
+
+IMAGE_UUID=$(sed -n 's/^IMAGE_UUID="\(.*\)"/\1/p' /etc/os-release)
+echo "${IMAGE_UUID}" > "${DESTDIR}/conf/image_uuid"
+
+exit 0
\ No newline at end of file
diff --git a/recipes-support/initramfs-config/files/initramfs.lsblk.hook b/recipes-support/initramfs-config/files/initramfs.lsblk.hook
new file mode 100644
index 0000000..cf32404
--- /dev/null
+++ b/recipes-support/initramfs-config/files/initramfs.lsblk.hook
@@ -0,0 +1,29 @@
+# This software is a part of ISAR.
+# Copyright (C) Siemens AG, 2020
+#
+# SPDX-License-Identifier: MIT
+
+#!/bin/sh
+PREREQ=""
+
+prereqs()
+{
+ echo "$PREREQ"
+}
+
+case $1 in
+prereqs)
+ prereqs
+ exit 0
+ ;;
+esac
+
+. /usr/share/initramfs-tools/scripts/functions
+. /usr/share/initramfs-tools/hook-functions
+
+if [ ! -x /usr/bin/lsblk ]; then
+ echo "Warning: couldn't find /usr/bin/lsblk!"
+ exit 0
+fi
+
+copy_exec /usr/bin/lsblk
diff --git a/recipes-support/initramfs-config/files/postinst.ext b/recipes-support/initramfs-config/files/postinst.ext
new file mode 100644
index 0000000..cdafa74
--- /dev/null
+++ b/recipes-support/initramfs-config/files/postinst.ext
@@ -0,0 +1,3 @@
+if [ -d /usr/share/secureboot ]; then
+ patch -s -p0 /usr/share/initramfs-tools/scripts/local /usr/share/secureboot/secure-boot-debian-local.patch
+fi
diff --git a/recipes-support/initramfs-config/files/postinst.tmpl b/recipes-support/initramfs-config/files/postinst.tmpl
new file mode 100644
index 0000000..008f68d
--- /dev/null
+++ b/recipes-support/initramfs-config/files/postinst.tmpl
@@ -0,0 +1,31 @@
+#!/bin/sh
+if [ -d /usr/share/secureboot ]; then
+ patch -s -p0 /usr/share/initramfs-tools/scripts/local /usr/share/secureboot/secure-boot-debian-local.patch
+fi
+
+INITRAMFS_CONF=/etc/initramfs-tools/initramfs.conf
+if [ -f ${INITRAMFS_CONF} ]; then
+ sed -i -E 's/(^MODULES=).*/\1${INITRAMFS_MODULES}/' ${INITRAMFS_CONF}
+ sed -i -E 's/(^BUSYBOX=).*/\1${INITRAMFS_BUSYBOX}/' ${INITRAMFS_CONF}
+ sed -i -E 's/(^COMPRESS=).*/\1${INITRAMFS_COMPRESS}/' ${INITRAMFS_CONF}
+ sed -i -E 's/(^KEYMAP=).*/\1${INITRAMFS_KEYMAP}/' ${INITRAMFS_CONF}
+ sed -i -E 's/(^DEVICE=).*/\1${INITRAMFS_NET_DEVICE}/' ${INITRAMFS_CONF}
+ sed -i -E 's/(^NFSROOT=).*/\1${INITRAMFS_NFSROOT}/' ${INITRAMFS_CONF}
+ sed -i -E 's/(^RUNSIZE=).*/\1${INITRAMFS_RUNSIZE}/' ${INITRAMFS_CONF}
+ if grep -Fxq "ROOT=" "${INITRAMFS_CONF}"; then
+ sed -i -E 's/(^ROOT=).*/\1${INITRAMFS_ROOT}/' ${INITRAMFS_CONF}
+ else
+ sed -i -E "\$aROOT=${INITRAMFS_ROOT}" ${INITRAMFS_CONF}
+ fi
+fi
+
+MODULES_LIST_FILE=/etc/initramfs-tools/modules
+if [ -f ${MODULES_LIST_FILE} ]; then
+ for modname in ${INITRAMFS_MODULE_LIST}; do
+ if ! grep -Fxq "$modname" "${MODULES_LIST_FILE}"; then
+ echo "$modname" >> "${MODULES_LIST_FILE}"
+ fi
+ done
+fi
+
+update-initramfs -v -u
diff --git a/recipes-support/initramfs-config/files/secure-boot-debian-local-patch b/recipes-support/initramfs-config/files/secure-boot-debian-local-patch
new file mode 100644
index 0000000..219578c
--- /dev/null
+++ b/recipes-support/initramfs-config/files/secure-boot-debian-local-patch
@@ -0,0 +1,79 @@
+--- local 2020-07-02 14:59:15.461895194 +0200
++++ ../../../../../../../../../../../recipes-support/initramfs-config/files/local 2020-07-02 14:58:58.405730914 +0200
+@@ -1,5 +1,4 @@
+ # Local filesystem mounting -*- shell-script -*-
+-
+ local_top()
+ {
+ if [ "${local_top_used}" != "yes" ]; then
+@@ -155,34 +154,47 @@
+ local_mount_root()
+ {
+ local_top
+- if [ -z "${ROOT}" ]; then
+- panic "No root device specified. Boot arguments must include a root= parameter."
+- fi
+- local_device_setup "${ROOT}" "root file system"
+- ROOT="${DEV}"
+-
+- # Get the root filesystem type if not set
+- if [ -z "${ROOTFSTYPE}" ] || [ "${ROOTFSTYPE}" = auto ]; then
+- FSTYPE=$(get_fstype "${ROOT}")
+- else
+- FSTYPE=${ROOTFSTYPE}
++ if [ ! -e /conf/image_uuid ]; then
++ panic "could not find image_uuid to select correct root file system"
+ fi
++ local INITRAMFS_IMAGE_UUID=$(cat /conf/image_uuid)
++ local partitions=$(blkid -o device)
++ for part in $partitions; do
++ if [ "$(blkid -p ${part} --match-types novfat -s USAGE -o value)" = "filesystem" ]; then
++ local_device_setup "${part}" "root file system"
++ ROOT="${DEV}"
++
++ # Get the root filesystem type if not set
++ if [ -z "${ROOTFSTYPE}" ] || [ "${ROOTFSTYPE}" = auto ]; then
++ FSTYPE=$(get_fstype "${ROOT}")
++ else
++ FSTYPE=${ROOTFSTYPE}
++ fi
+
+- local_premount
++ local_premount
+
+- if [ "${readonly?}" = "y" ]; then
+- roflag=-r
+- else
+- roflag=-w
+- fi
++ if [ "${readonly?}" = "y" ]; then
++ roflag=-r
++ else
++ roflag=-w
++ fi
++ checkfs "${ROOT}" root "${FSTYPE}"
+
+- checkfs "${ROOT}" root "${FSTYPE}"
++ # Mount root
++ # shellcheck disable=SC2086
++ if mount ${roflag} ${FSTYPE:+-t "${FSTYPE}"} ${ROOTFLAGS} "${ROOT}" "${rootmnt?}"; then
++ if [ -e "${rootmnt?}"/etc/os-release ]; then
++ image_uuid=$(sed -n 's/^IMAGE_UUID=//p' "${rootmnt?}"/etc/os-release | tr -d '"' )
++ if [ "${INITRAMFS_IMAGE_UUID}" = "${image_uuid}" ]; then
++ return
++ fi
++ fi
++ umount "${rootmnt?}"
++ fi
++ fi
++ done
++ panic "Could not find ROOTFS with matching UUID $INITRAMFS_IMAGE_UUID"
+
+- # Mount root
+- # shellcheck disable=SC2086
+- if ! mount ${roflag} ${FSTYPE:+-t "${FSTYPE}"} ${ROOTFLAGS} "${ROOT}" "${rootmnt?}"; then
+- panic "Failed to mount ${ROOT} as root file system."
+- fi
+ }
+
+ local_mount_fs()
diff --git a/recipes-support/initramfs-config/initramfs-abrootfs-secureboot_0.1.bb b/recipes-support/initramfs-config/initramfs-abrootfs-secureboot_0.1.bb
new file mode 100644
index 0000000..0be9871
--- /dev/null
+++ b/recipes-support/initramfs-config/initramfs-abrootfs-secureboot_0.1.bb
@@ -0,0 +1,38 @@
+#
+# CIP Core, generic profile
+#
+# Copyright (c) Siemens AG, 2020
+#
+# Authors:
+# Quirin Gylstorff <quirin.gylstorff@...>
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-support/initramfs-config/initramfs-config.inc
+
+FILESPATH =. "${LAYERDIR_isar-siemens}/recipes-support/initramfs-config/files:"
+
+DEBIAN_DEPENDS += ", busybox, patch"
+
+SRC_URI += "file://postinst.ext \
+ file://initramfs.lsblk.hook \
+ file://initramfs.image_uuid.hook \
+ file://secure-boot-debian-local-patch"
+
+INITRAMFS_BUSYBOX = "y"
+
+do_install() {
+ # add patch for local to /usr/share/secure boot
+ TARGET=${D}/usr/share/secureboot
+ install -m 0755 -d ${TARGET}
+ install -m 0644 ${WORKDIR}/secure-boot-debian-local-patch ${TARGET}/secure-boot-debian-local.patch
+ # patch postinst
+ sed -i -e '/configure)/r ${WORKDIR}/postinst.ext' ${WORKDIR}/postinst
+
+ # add hooks for secure boot
+ HOOKS=${D}/etc/initramfs-tools/hooks
+install -m 0755 -d ${HOOKS}
+ install -m 0740 ${WORKDIR}/initramfs.lsblk.hook ${HOOKS}/lsblk.hook
+ install -m 0740 ${WORKDIR}/initramfs.image_uuid.hook ${HOOKS}/image_uuid.hook
Fixed this indention while merging.

+}
+addtask do_install after do_transform_template
Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux


[PATCH 4.19.y-cip 0/7] Add IPMMU/SYS-DMAC/GPIO/EAVB Support on R8A774E1

Biju Das <biju.das.jz@...>
 

This patch series add support for IPMMU/SYS-DMAC/GPIO/EAVB on
HiHope RZ/G2H board based on R8A774E1 SoC.

This patches in this series are cherry-picked from mainline.

This patch series depend upon [1]
[1]: https://patchwork.kernel.org/project/cip-dev/list/?series=336489

Lad Prabhakar (2):
dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support
dt-bindings: dma: renesas,rcar-dmac: Document R8A774E1 bindings

Marian-Cristian Rotariu (5):
iommu/ipmmu-vmsa: Hook up R8A774E1 DT matching code
arm64: dts: renesas: r8a774e1: Add IPMMU device nodes
arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes
arm64: dts: renesas: r8a774e1: Add GPIO device nodes
arm64: dts: renesas: r8a774e1: Add Ethernet AVB node

.../bindings/dma/renesas,rcar-dmac.txt | 1 +
.../bindings/iommu/renesas,ipmmu-vmsa.txt | 1 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 361 +++++++++++++++++-
drivers/iommu/ipmmu-vmsa.c | 5 +
4 files changed, 349 insertions(+), 19 deletions(-)

--
2.17.1


[PATCH 4.19.y-cip 7/7] arm64: dts: renesas: r8a774e1: Add Ethernet AVB node

Biju Das <biju.das.jz@...>
 

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>

commit 8d54886cbb4efb6e7a35ee1c7d0e9d91b4c73ca9 upstream.

This patch adds the SoC specific part of the Ethernet AVB
device tree node.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/1594676120-5862-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 41 +++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 17b69d9a634c..d76aec73aa28 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -695,12 +695,49 @@
};

avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a774e1",
+ "renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
-
- /* placeholder */
};

can0: can@e6c30000 {
--
2.17.1


[PATCH 4.19.y-cip 6/7] arm64: dts: renesas: r8a774e1: Add GPIO device nodes

Biju Das <biju.das.jz@...>
 

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>

commit 43b0c905949735e40b1c90fc354ff2944283103d upstream.

Add GPIO device nodes to the DT of the r8a774e1 SoC.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/1594676120-5862-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 73 +++++++++++++++++------
1 file changed, 56 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 4bd660e184ac..17b69d9a634c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -246,84 +246,123 @@
};

gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 0 16>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
};

gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 32 29>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
};

gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 64 15>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
};

gpio3: gpio@e6053000 {
- /* placeholder */
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 96 16>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
};

gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 128 18>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
};

gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 160 26>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
};

gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 192 32>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 906>;
};

gpio7: gpio@e6055800 {
+ compatible = "renesas,gpio-r8a774e1",
+ "renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 224 4>;
#interrupt-cells = <2>;
interrupt-controller;
-
- /* placeholder */
+ clocks = <&cpg CPG_MOD 905>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 905>;
};

pfc: pin-controller@e6060000 {
--
2.17.1


[PATCH 4.19.y-cip 5/7] arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes

Biju Das <biju.das.jz@...>
 

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>

commit f1bf8ff8d58360d396d01f4aab6316e28e75d4b7 upstream.

Add sys-dmac[0-2] device nodes for RZ/G2H (R8A774E1) SoC.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/1594676120-5862-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 126 ++++++++++++++++++++++
1 file changed, 126 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index a50902c8173d..4bd660e184ac 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -408,6 +408,132 @@
/* placeholder */
};

+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+ <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+ <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+ <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+ <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+ <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+ <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+ <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+ <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+ <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+ <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+ <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+ <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+ <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+ <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a774e1",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+ <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+ <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+ <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+ <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+ <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ };
+
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xe6740000 0 0x1000>;
--
2.17.1


[PATCH 4.19.y-cip 4/7] dt-bindings: dma: renesas,rcar-dmac: Document R8A774E1 bindings

Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>

commit 09b4db279758dd3d5bb235605e985b99e7bc1a93 upstream.

Renesas RZ/G2H (R8A774E1) SoC also has the R-Car gen3 compatible
DMA controllers, therefore document RZ/G2H specific bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/1594676120-5862-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@...>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@...>
---
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index b6927eb3e6f2..59d2ad3d39dd 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -22,6 +22,7 @@ Required Properties:
- "renesas,dmac-r8a774a1" (RZ/G2M)
- "renesas,dmac-r8a774b1" (RZ/G2N)
- "renesas,dmac-r8a774c0" (RZ/G2E)
+ - "renesas,dmac-r8a774e1" (RZ/G2H)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
--
2.17.1


[PATCH 4.19.y-cip 3/7] arm64: dts: renesas: r8a774e1: Add IPMMU device nodes

Biju Das <biju.das.jz@...>
 

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>

commit 615d1a9ebcfb90d5ddbfd887d42eda5dc8b03303 upstream.

Add RZ/G2H (R8A774E1) IPMMU nodes.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/1594676120-5862-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 121 ++++++++++++++++++++++
1 file changed, 121 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index eb7226e8e892..a50902c8173d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -408,6 +408,127 @@
/* placeholder */
};

+ ipmmu_ds0: iommu@e6740000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xe6740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ds1: iommu@e7740000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 1>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_hc: iommu@e6570000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xe6570000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 2>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: iommu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mp0: iommu@ec670000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xec670000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 4>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_pv0: iommu@fd800000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfd800000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 6>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_pv1: iommu@fd950000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfd950000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 7>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_pv2: iommu@fd960000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfd960000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 8>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_pv3: iommu@fd970000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfd970000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 9>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: iommu@fe6b0000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A774E1_PD_A3VC>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc1: iommu@fe6f0000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfe6f0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 13>;
+ power-domains = <&sysc R8A774E1_PD_A3VC>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: iommu@febd0000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi1: iommu@febe0000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfebe0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 15>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vp0: iommu@fe990000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfe990000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 16>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vp1: iommu@fe980000 {
+ compatible = "renesas,ipmmu-r8a774e1";
+ reg = <0 0xfe980000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 17>;
+ power-domains = <&sysc R8A774E1_PD_A3VP>;
+ #iommu-cells = <1>;
+ };
+
avb: ethernet@e6800000 {
reg = <0 0xe6800000 0 0x800>;
#address-cells = <1>;
--
2.17.1


[PATCH 4.19.y-cip 2/7] iommu/ipmmu-vmsa: Hook up R8A774E1 DT matching code

Biju Das <biju.das.jz@...>
 

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>

commit 4b2aa7a6f9b793cadbda898476c8a16d374f1b3a upstream.

Add support for RZ/G2H (R8A774E1) SoC IPMMUs.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Link: https://lore.kernel.org/r/1594722055-9298-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Joerg Roedel <jroedel@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/iommu/ipmmu-vmsa.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
index ea4d19da9865..dfc90ca3f0fe 100644
--- a/drivers/iommu/ipmmu-vmsa.c
+++ b/drivers/iommu/ipmmu-vmsa.c
@@ -761,6 +761,7 @@ static const struct soc_device_attribute soc_rcar_gen3[] = {
{ .soc_id = "r8a774a1", },
{ .soc_id = "r8a774b1", },
{ .soc_id = "r8a774c0", },
+ { .soc_id = "r8a774e1", },
{ .soc_id = "r8a7795", },
{ .soc_id = "r8a7796", },
{ .soc_id = "r8a77965", },
@@ -772,6 +773,7 @@ static const struct soc_device_attribute soc_rcar_gen3[] = {
static const struct soc_device_attribute soc_rcar_gen3_whitelist[] = {
{ .soc_id = "r8a774b1", },
{ .soc_id = "r8a774c0", },
+ { .soc_id = "r8a774e1", },
{ .soc_id = "r8a7795", .revision = "ES3.*" },
{ .soc_id = "r8a77965", },
{ .soc_id = "r8a77990", },
@@ -975,6 +977,9 @@ static const struct of_device_id ipmmu_of_ids[] = {
}, {
.compatible = "renesas,ipmmu-r8a774c0",
.data = &ipmmu_features_rcar_gen3,
+ }, {
+ .compatible = "renesas,ipmmu-r8a774e1",
+ .data = &ipmmu_features_rcar_gen3,
}, {
.compatible = "renesas,ipmmu-r8a7795",
.data = &ipmmu_features_rcar_gen3,
--
2.17.1


[PATCH 4.19.y-cip 1/7] dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support

Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>

commit 8a71c743bf5ecdcfb439662e4cef89d7b1132495 upstream.

Document RZ/G2H (R8A774E1) SoC bindings.

Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/1594676120-5862-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Rob Herring <robh@...>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@...>
---
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
index 56faf8dd0077..e2bc780b803c 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
@@ -16,6 +16,7 @@ Required Properties:
- "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
- "renesas,ipmmu-r8a774b1" for the R8A774B1 (RZ/G2N) IPMMU.
- "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
+ - "renesas,ipmmu-r8a774e1" for the R8A774E1 (RZ/G2H) IPMMU.
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
--
2.17.1


[PATCH 24/36] pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions

Biju Das <biju.das.jz@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 0cbdf1b876243c73a795783ce69004302e250a43 upstream.

Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revision ES1.x of the R-Car H3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 42 ++++++++++++++++++++++++
1 file changed, 42 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 97a6b0221855..aea009f40f49 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -3812,6 +3812,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};

+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4165,6 +4195,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@@ -4635,6 +4669,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};

+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
@@ -4707,6 +4748,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
--
2.17.1


[PATCH 36/36] arm64: dts: renesas: Add HiHope RZ/G2H sub board support

Biju Das <biju.das.jz@...>
 

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>

commit adbe62e93c1e793ad08d5e913151137b6c24daa4 upstream.

The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board.
These boards are identical with the ones for RZ/G2M[N].

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/1594230511-24790-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +-
.../boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 15 +++++++++++++++
3 files changed, 17 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 9c2942510ab5..73cf57a3919b 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
r8a774c0-ek874-idk-2121wr.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
+dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index acfcfd050a6c..178401a34cbf 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
+ * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 000000000000..265355e0de5f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2H with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+ "renesas,r8a774e1";
+};
--
2.17.1


[PATCH 27/36] pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pins

Biju Das <biju.das.jz@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 42ee6c3395465cea948a462b4605fc7fa53e3704 upstream.

Update the R-Car H3 ES2.0 and later pin control driver to use the new
macros for describing pins without GPIO functionality. This replaces
the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39
BGA package) by symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 313 +++++++++++++--------------
1 file changed, 154 insertions(+), 159 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 054fec90eded..3172ef6a9b20 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -30,6 +30,52 @@
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
+
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@@ -1509,67 +1555,16 @@ static const u16 pinmux_data[] = {
};

/*
- * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
- * Physical layout rows: A - AW, cols: 1 - 39.
+ * Pins not associated with a GPIO port.
*/
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
-#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
-#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+enum {
+ GP_ASSIGN_LAST(),
+ NOGP_ALL(),
+};

static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
-
- /*
- * Pins not associated with a GPIO port.
- *
- * The pin positions are different between different r8a7795
- * packages, all that is needed for the pfc driver is a unique
- * number for each pin. To this end use the pin layout from
- * R-Car H3SiP to calculate a unique number for each pin.
- */
- SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
+ PINMUX_NOGP_ALL(),
};

/* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -1717,7 +1712,7 @@ static const unsigned int avb_phy_int_mux[] = {
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
- RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
+ RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
@@ -1730,11 +1725,11 @@ static const unsigned int avb_mii_pins[] = {
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
- PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
- PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
- PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
- PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
- PIN_NUMBER('A', 12),
+ PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
+ PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
+ PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
+ PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
+ PIN_AVB_TXCREFCLK,

};
static const unsigned int avb_mii_mux[] = {
@@ -5665,44 +5660,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {

static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
- { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
- { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
- { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
- { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
- { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
- { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
- { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
- { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
+ { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
+ { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
+ { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
+ { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
+ { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
+ { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
+ { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
+ { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
- { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
- { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
- { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
- { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
- { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
- { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
- { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
- { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
+ { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
+ { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
+ { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
+ { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
+ { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
+ { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
+ { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
+ { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
- { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
- { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
- { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
- { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
- { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
- { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
- { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
- { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
+ { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
+ { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
+ { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
+ { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
+ { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
+ { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
+ { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
+ { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
- { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
- { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
- { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
- { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
- { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
- { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
- { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
- { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
+ { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
+ { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
+ { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
+ { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
+ { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
+ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
+ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
+ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@@ -5756,7 +5751,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
- { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
+ { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@@ -5775,30 +5770,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
- { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
- { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
- { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
- { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
- { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
- { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
- { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
+ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
+ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
+ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
+ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
+ { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
+ { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
- { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
- { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
- { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
- { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
+ { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
+ { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
+ { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
+ { PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
- { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
- { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
- { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
- { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
- { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
- { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
- { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
- { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
+ { PIN_TDO, 28, 2 }, /* TDO */
+ { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
+ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
+ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
+ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
+ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
+ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
+ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@@ -5867,7 +5862,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
- { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
+ { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@@ -5940,35 +5935,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc

static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
- [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
- [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
- [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
- [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
- [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
- [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
- [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
- [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
- [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
- [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
- [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
- [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
- [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
- [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
- [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
- [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
- [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
- [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
- [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
- [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
- [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
- [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
- [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
- [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
- [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
- [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
- [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
- [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
- [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
+ [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
+ [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
+ [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
+ [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
+ [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
+ [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
+ [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
+ [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
+ [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
+ [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
+ [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
+ [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
+ [12] = PIN_RPC_INT_N, /* RPC_INT# */
+ [13] = PIN_RPC_WP_N, /* RPC_WP# */
+ [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
+ [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
+ [16] = PIN_AVB_RXC, /* AVB_RXC */
+ [17] = PIN_AVB_RD0, /* AVB_RD0 */
+ [18] = PIN_AVB_RD1, /* AVB_RD1 */
+ [19] = PIN_AVB_RD2, /* AVB_RD2 */
+ [20] = PIN_AVB_RD3, /* AVB_RD3 */
+ [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
+ [22] = PIN_AVB_TXC, /* AVB_TXC */
+ [23] = PIN_AVB_TD0, /* AVB_TD0 */
+ [24] = PIN_AVB_TD1, /* AVB_TD1 */
+ [25] = PIN_AVB_TD2, /* AVB_TD2 */
+ [26] = PIN_AVB_TD3, /* AVB_TD3 */
+ [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
+ [28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@@ -6017,7 +6012,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
- [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
+ [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
@@ -6038,20 +6033,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
- [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
- [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
+ [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
+ [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
- [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
- [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
- [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
- [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
- [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
- [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
- [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
- [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
+ [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
+ [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
+ [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
+ [ 3] = PIN_EXTALR, /* EXTALR*/
+ [ 4] = PIN_TRST_N, /* TRST# */
+ [ 5] = PIN_TCK, /* TCK */
+ [ 6] = PIN_TMS, /* TMS */
+ [ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
- [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
+ [ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@@ -6116,7 +6111,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
- [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
+ [ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
--
2.17.1


[PATCH 25/36] pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions

Biju Das <biju.das.jz@...>
 

From: Geert Uytterhoeven <geert+renesas@...>

commit 9141d4558fcc635c4ec3b5ddd99f24d8df7fe6e0 upstream.

Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revisions ES2.x and later of the R-Car H3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Reviewed-by: Simon Horman <horms+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 42 ++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 944dfd943541..054fec90eded 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -3901,6 +3901,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};

+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4451,6 +4481,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@@ -4946,6 +4980,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};

+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
static const char * const usb0_groups[] = {
"usb0",
};
@@ -5048,6 +5089,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
--
2.17.1

3461 - 3480 of 8688