[PATCH 4.19.y-cip 10/10] arm64: dts: renesas: r8a774e1: Add CAN[FD] support
Biju Das <biju.das.jz@...>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 8e340e7560d1d4db3b7ed5c010d3460de8ff0c1e upstream. Add CAN[01] and CANFD support to RZ/G2H (R8A774E1) SoC specific dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1594811350-14066-21-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 56 +++++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index c4f12544703d..af090cd90f5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -34,6 +34,13 @@ clock-frequency = <0>; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; @@ -941,17 +948,60 @@ }; can0: can@e6c30000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; - - /* placeholder */ }; can1: can@e6c38000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; + }; - /* placeholder */ + canfd: can@e66c0000 { + compatible = "renesas,r8a774e1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; pwm0: pwm@e6e30000 { -- 2.17.1
|
|
[PATCH 4.19.y-cip 09/10] can: rcar_can: Remove unused platform data support
Biju Das <biju.das.jz@...>
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 30cc0ed73e3390af7c5573b159826e8162f09fe7 upstream. All R-Car platforms use DT for describing CAN controllers. R-Car CAN platform data support was never used in any upstream kernel. Move the Clock Select Register settings enum into the driver, and remove platform data support and the corresponding header file. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- drivers/net/can/rcar/rcar_can.c | 22 +++++++++------------- include/linux/can/platform/rcar_can.h | 18 ------------------ 2 files changed, 9 insertions(+), 31 deletions(-) delete mode 100644 include/linux/can/platform/rcar_can.h diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c index 771a46083739..bfb674193a21 100644 --- a/drivers/net/can/rcar/rcar_can.c +++ b/drivers/net/can/rcar/rcar_can.c @@ -19,11 +19,17 @@ #include <linux/can/led.h> #include <linux/can/dev.h> #include <linux/clk.h> -#include <linux/can/platform/rcar_can.h> #include <linux/of.h> #define RCAR_CAN_DRV_NAME "rcar_can" +/* Clock Select Register settings */ +enum CLKR { + CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ + CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ + CLKR_CLKEXT = 3, /* Externally input clock */ +}; + #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ BIT(CLKR_CLKEXT)) @@ -740,7 +746,6 @@ static const char * const clock_names[] = { static int rcar_can_probe(struct platform_device *pdev) { - struct rcar_can_platform_data *pdata; struct rcar_can_priv *priv; struct net_device *ndev; struct resource *mem; @@ -749,17 +754,8 @@ static int rcar_can_probe(struct platform_device *pdev) int err = -ENODEV; int irq; - if (pdev->dev.of_node) { - of_property_read_u32(pdev->dev.of_node, - "renesas,can-clock-select", &clock_select); - } else { - pdata = dev_get_platdata(&pdev->dev); - if (!pdata) { - dev_err(&pdev->dev, "No platform data provided!\n"); - goto fail; - } - clock_select = pdata->clock_select; - } + of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select", + &clock_select); irq = platform_get_irq(pdev, 0); if (irq < 0) { diff --git a/include/linux/can/platform/rcar_can.h b/include/linux/can/platform/rcar_can.h deleted file mode 100644 index a43dcd0cf79e..000000000000 --- a/include/linux/can/platform/rcar_can.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CAN_PLATFORM_RCAR_CAN_H_ -#define _CAN_PLATFORM_RCAR_CAN_H_ - -#include <linux/types.h> - -/* Clock Select Register settings */ -enum CLKR { - CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ - CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ - CLKR_CLKEXT = 3 /* Externally input clock */ -}; - -struct rcar_can_platform_data { - enum CLKR clock_select; /* Clock source select */ -}; - -#endif /* !_CAN_PLATFORM_RCAR_CAN_H_ */ -- 2.17.1
|
|
[PATCH 4.19.y-cip 08/10] arm64: dts: renesas: r8a774e1: Add TMU device nodes
Biju Das <biju.das.jz@...>
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 58eb575cf0450bab583dc4009a39644bf98754cc upstream. This patch adds TMU[01234] device tree nodes to the r8a774e1 SoC specific DT. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594811350-14066-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 264f3b7e3c11..c4f12544703d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -542,6 +542,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c2: i2c@e6510000 { reg = <0 0xe6510000 0 0x40>; #address-cells = <1>; -- 2.17.1
|
|
[PATCH 4.19.y-cip 07/10] arm64: dts: renesas: r8a774e1: Add CMT device nodes
Biju Das <biju.das.jz@...>
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit c6c4b7defd391da84da0ac640df0da2a13680a9e upstream. This patch adds the CMT[0123] device tree nodes to the r8a774e1 SoC specific DT. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594811350-14066-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 70c5e28e201e..264f3b7e3c11 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -421,6 +421,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774e1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a774e1-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- 2.17.1
|
|
[PATCH 4.19.y-cip 06/10] arm64: dts: renesas: r8a774e1: Add RZ/G2H thermal support
Biju Das <biju.das.jz@...>
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 6dd733679911598354b0445f07a3e6c3141c865c upstream. Add thermal support for R8A774E1 (RZ/G2H) SoC. Based on the work done for r8a774a1 SoC. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594811350-14066-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 81 +++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 3a3490adc8a0..70c5e28e201e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -442,6 +442,20 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a774e1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; #interrupt-cells = <2>; @@ -1003,6 +1017,73 @@ }; }; + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <6313>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <6313>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <6313>; + + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, -- 2.17.1
|
|
[PATCH 4.19.y-cip 05/10] thermal: rcar_gen3_thermal: Add r8a774e1 support
Biju Das <biju.das.jz@...>
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit 947d85f00c030aa88eef0c065b6f4636547257d7 upstream. Add r8a774e1 specific compatible string. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/1594811350-14066-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/thermal/rcar_gen3_thermal.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 92758445c574..9ebcbb07bbc0 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -314,6 +314,10 @@ static const struct of_device_id rcar_gen3_thermal_dt_ids[] = { .compatible = "renesas,r8a774b1-thermal", .data = &rcar_gen3_ths_tj_1, }, + { + .compatible = "renesas,r8a774e1-thermal", + .data = &rcar_gen3_ths_tj_1, + }, { .compatible = "renesas,r8a7795-thermal", .data = &rcar_gen3_ths_tj_1, -- 2.17.1
|
|
[PATCH 4.19.y-cip 04/10] thermal/drivers/rcar_gen3: Fix undefined temperature if negative
Biju Das <biju.das.jz@...>
From: Dien Pham <dien.pham.ry@renesas.com>
commit 5f8f06425a0dcdad7bedbb77e67f5c65ab4dacfc upstream. As description for DIV_ROUND_CLOSEST in file include/linux/kernel.h. "Result is undefined for negative divisors if the dividend variable type is unsigned and for negative dividends if the divisor variable type is unsigned." In current code, the FIXPT_DIV uses DIV_ROUND_CLOSEST but has not checked sign of divisor before using. It makes undefined temperature value in case the value is negative. This patch fixes to satisfy DIV_ROUND_CLOSEST description and fix bug too. Note that the variable name "reg" is not good because it should be the same type as rcar_gen3_thermal_read(). However, it's better to rename the "reg" in a further patch as cleanup. Signed-off-by: Van Do <van.do.xw@renesas.com> Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> [shimoda: minor fixes, add Fixes tag] Fixes: 564e73d283af ("thermal: rcar_gen3_thermal: Add R-Car Gen3 thermal driver") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Niklas Soderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Soderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/1593085099-2057-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/thermal/rcar_gen3_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 166cadf4bf02..92758445c574 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -167,7 +167,7 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int *temp) { struct rcar_gen3_thermal_tsc *tsc = devdata; int mcelsius, val; - u32 reg; + int reg; /* Read register and convert to mili Celsius */ reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK; -- 2.17.1
|
|
[PATCH 4.19.y-cip 03/10] thermal: rcar_gen3_thermal: Generate interrupt when temperature changes
Biju Das <biju.das.jz@...>
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
commit 267c4d8d132c8646fc90a58d40e3117656a4e9b5 upstream. The desired behavior of the driver is to generate an interrupt and call thermal_zone_device_update() as soon as the temperature have changed more then one degree. When the set_trips operation was implemented it was believed that the trip window set by the framework would move around the current temperature and the hysteresis value described in devicetree. The behavior of the framework is however to set a window based on the trip points described in devicetree. Remove the set_trips operation which was not used correctly and update the temperatures that triggers interrupts directly from the interrupt handler. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200212224917.737314-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/thermal/rcar_gen3_thermal.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index e7a0c7fc9897..166cadf4bf02 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -81,8 +81,6 @@ struct rcar_gen3_thermal_tsc { void __iomem *base; struct thermal_zone_device *zone; struct equation_coefs coef; - int low; - int high; int tj_t; int id; /* thermal channel id */ }; @@ -204,12 +202,14 @@ static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc *tsc, return INT_FIXPT(val); } -static int rcar_gen3_thermal_set_trips(void *devdata, int low, int high) +static int rcar_gen3_thermal_update_range(struct rcar_gen3_thermal_tsc *tsc) { - struct rcar_gen3_thermal_tsc *tsc = devdata; + int temperature, low, high; + + rcar_gen3_thermal_get_temp(tsc, &temperature); - low = clamp_val(low, -40000, 120000); - high = clamp_val(high, -40000, 120000); + low = temperature - MCELSIUS(1); + high = temperature + MCELSIUS(1); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1, rcar_gen3_thermal_mcelsius_to_temp(tsc, low)); @@ -217,15 +217,11 @@ static int rcar_gen3_thermal_set_trips(void *devdata, int low, int high) rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP2, rcar_gen3_thermal_mcelsius_to_temp(tsc, high)); - tsc->low = low; - tsc->high = high; - return 0; } static const struct thermal_zone_of_device_ops rcar_gen3_tz_of_ops = { .get_temp = rcar_gen3_thermal_get_temp, - .set_trips = rcar_gen3_thermal_set_trips, }; static void rcar_thermal_irq_set(struct rcar_gen3_thermal_priv *priv, bool on) @@ -246,9 +242,11 @@ static irqreturn_t rcar_gen3_thermal_irq(int irq, void *data) for (i = 0; i < priv->num_tscs; i++) { status = rcar_gen3_thermal_read(priv->tscs[i], REG_GEN3_IRQSTR); rcar_gen3_thermal_write(priv->tscs[i], REG_GEN3_IRQSTR, 0); - if (status) + if (status) { + rcar_gen3_thermal_update_range(priv->tscs[i]); thermal_zone_device_update(priv->tscs[i]->zone, THERMAL_EVENT_UNSPECIFIED); + } } return IRQ_HANDLED; @@ -451,6 +449,8 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev) if (ret < 0) goto error_unregister; + rcar_gen3_thermal_update_range(tsc); + dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret); } @@ -489,7 +489,7 @@ static int __maybe_unused rcar_gen3_thermal_resume(struct device *dev) struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; priv->thermal_init(tsc); - rcar_gen3_thermal_set_trips(tsc, tsc->low, tsc->high); + rcar_gen3_thermal_update_range(tsc); } rcar_thermal_irq_set(priv, true); -- 2.17.1
|
|
[PATCH 4.19.y-cip 02/10] thermal: rcar_gen3_thermal: Remove temperature bound
Biju Das <biju.das.jz@...>
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
commit 0f510a2457cbbba18a98492bab1bf540be57ebd1 upstream. The hardware manual states that the operation of the sensor is not guaranteed with temperatures above 125°C, not that the readings are invalid. Remove the bound check and try to deliver temperature readings even if we are outside the guaranteed operation range. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200117160554.3812787-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/thermal/rcar_gen3_thermal.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 42ec69d29540..e7a0c7fc9897 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -182,9 +182,7 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int *temp) tsc->coef.a2); mcelsius = FIXPT_TO_MCELSIUS(val); - /* Make sure we are inside specifications */ - if ((mcelsius < MCELSIUS(-40)) || (mcelsius > MCELSIUS(125))) - return -EIO; + /* Guaranteed operating range is -40C to 125C. */ /* Round value to device granularity setting */ *temp = rcar_gen3_thermal_round(mcelsius); -- 2.17.1
|
|
[PATCH 4.19.y-cip 01/10] arm64: dts: renesas: r8a774e1: Add operating points
Biju Das <biju.das.jz@...>
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit d18dbce4e8c02634866dc80c7873e6121fcae970 upstream. The RZ/G2H (r8a774e1) comes with two clusters of processors, similarly to the r8a774a1. The first cluster is made of A57s, the second cluster is made of A53s. The operating points for the cluster with the A57s are: Frequency | Voltage ----------|--------- 500 MHz | 0.82V 1.0 GHz | 0.82V 1.5 GHz | 0.82V The operating points for the cluster with the A53s are: Frequency | Voltage ----------|--------- 800 MHz | 0.82V 1.0 GHz | 0.82V 1.2 GHz | 0.82V This patch adds the definitions for the operating points to the SoC specific DT. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594811350-14066-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index d76aec73aa28..3a3490adc8a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -34,6 +34,49 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -79,6 +122,7 @@ enable-method = "psci"; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -91,6 +135,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -103,6 +148,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -115,6 +161,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -129,6 +176,7 @@ #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; @@ -140,6 +188,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; @@ -151,6 +200,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; @@ -162,6 +212,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; -- 2.17.1
|
|
[PATCH 4.19.y-cip 00/10] Add OPP/Thermal/Timer/CAN[FD] support
Biju Das <biju.das.jz@...>
This patch series add RZ/G2H SoC support for OPP/Thermal/Timer/CAN[FD]
to 4.19.y cip kernel. All the patches in this series are cherry-picked from ML. This patch series depend upon [1] [1]: https://patchwork.kernel.org/project/cip-dev/list/?series=336609 Dien Pham (1): thermal/drivers/rcar_gen3: Fix undefined temperature if negative Geert Uytterhoeven (1): can: rcar_can: Remove unused platform data support Lad Prabhakar (1): arm64: dts: renesas: r8a774e1: Add CAN[FD] support Marian-Cristian Rotariu (5): arm64: dts: renesas: r8a774e1: Add operating points thermal: rcar_gen3_thermal: Add r8a774e1 support arm64: dts: renesas: r8a774e1: Add RZ/G2H thermal support arm64: dts: renesas: r8a774e1: Add CMT device nodes arm64: dts: renesas: r8a774e1: Add TMU device nodes Niklas Söderlund (2): thermal: rcar_gen3_thermal: Remove temperature bound thermal: rcar_gen3_thermal: Generate interrupt when temperature changes arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 323 +++++++++++++++++++++- drivers/net/can/rcar/rcar_can.c | 22 +- drivers/thermal/rcar_gen3_thermal.c | 34 +-- include/linux/can/platform/rcar_can.h | 18 -- 4 files changed, 347 insertions(+), 50 deletions(-) delete mode 100644 include/linux/can/platform/rcar_can.h -- 2.17.1
|
|
Re: [isar-cip-core][PATCH 1/2] ci: Rewrite using extends
Jan Kiszka
On 25.08.20 07:33, nobuhiro1.iwamatsu@toshiba.co.jp wrote:
Hi,So we need to avoid that for now, I guess. Back to single-job build, or-----Original Message-----<snip> do we have an alternative download source? The wic image names changed, and that broke compression and uploading.I don't have no idea about this. Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux
|
|
Re: [isar-cip-core][PATCH 1/2] ci: Rewrite using extends
Nobuhiro Iwamatsu
Hi,
toggle quoted messageShow quoted text
-----Original Message-----<snip> This may be a burden on kernel.org as snapshot reconstructs the imagebuild/tmp/work/cip-core-*/linux-cip*/*/linux-cip-*/debian/linux-image-cip*/usr/lib/linux-image-*/$DTB-if [ -n "$DTB" ]; then on the server side. I'm not sure, when downloading images continuously, access may be controlled by kernel.org. I don't have no idea about this. If we retry the test, it is successful and there may be other causes. Best regards, Nobuhiro --
|
|
Re: [isar-cip-core][PATCH 1/2] ci: Rewrite using extends
Jan Kiszka
On 21.08.20 18:44, Jan Kiszka wrote:
On 21.08.20 17:04, Jan Kiszka wrote:Ping - or should I revert those two for now?On 20.08.20 10:24, Nobuhiro Iwamatsu wrote:And I'm afraid there is more broken, namely in the deployment that isSigned-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>Unfortunately, this scale out to multiple jobs seem to cause download Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux
|
|
Re: [PATCH 4.19.y-cip 01/12] arm64: dts: renesas: r8a774a1-hihope-rzg2m[-ex/-ex-idk-1110wr]: Rename HiHope RZ/G2M boards
Biju Das <biju.das.jz@...>
Hi Pavel,
Thanks for the feedback. Subject: Re: [PATCH 4.19.y-cip 01/12] arm64: dts: renesas: r8a774a1-hihope-OK. Either README.cip or " by including more information on the reference hardware and test information on CIP wiki." as suggested by Nobuhiro. Please let us know, How do we want to proceed? Cheers, Biju Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
|
|
Re: [isar-cip-core][PATCH v4 3/6] secure-boot: select boot partition in initramfs
Quirin Gylstorff
On 8/21/20 4:45 PM, Jan Kiszka wrote:
On 21.08.20 11:55, Q. Gylstorff wrote:Thanks.From: Quirin Gylstorff <quirin.gylstorff@siemens.com>Fixed this indention while merging. --+}Jan Quirin
|
|
Re: [PATCH 4.19.y-cip 00/12] Support RZ/G2[MN] rev4 board
Nobuhiro Iwamatsu
Hi,
toggle quoted messageShow quoted text
-----Original Message-----Or I think we can do this by including more information on the reference hardware and test information on CIP wiki. Best regards, Nobuhiro --
|
|
Re: [PATCH 4.19.y-cip 0/7] Add IPMMU/SYS-DMAC/GPIO/EAVB Support on R8A774E1
Nobuhiro Iwamatsu
Hi,
toggle quoted messageShow quoted text
-----Original Message-----I have reviewed this patch series. I didn't see any problems. Best regards, Nobuhiro
|
|
Re: [PATCH 00/36] Add Hihope RZ/G2H basic board support
Nobuhiro Iwamatsu
Hi,
toggle quoted messageShow quoted text
-----Original Message-----I have reviewed this patch series. I didn't see any problems. Best regards, Nobuhiro
|
|
Re: [PATCH 4.19.y-cip 00/12] Support RZ/G2[MN] rev4 board
Pavel Machek
Hi!
*** gpg4o | The signature of this email could not be verified because the Technically yes, it would cause problems. However this seems to beYes, it is upstream problem, and should be fixed upstream. And no, not even upgrading kernel versions should break anything. lab-cip-renesas uses rev4 boards, so from a CIP testing point ofOk, good to know, it seems -rev2 boards are kind of rare? I guess we could create "README.cip" explaining such non-standard issues, and mention it in release changelog. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
|
|