Date   

[PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support

Lad Prabhakar
 

Hi All,

This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.

All the patches have been cherry-picked from mainline kernel
v5.10-rc2.

Cheers,
Prabhakar

Lad Prabhakar (6):
arm64: dts: renesas: r8a774e1: Add PCIe device nodes
arm64: dts: renesas: r8a774e1: Add SATA controller node
dt-bindings: pci: rcar-pci-ep: Document r8a774e1
arm64: dts: renesas: r8a774e1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller
arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata

.../devicetree/bindings/pci/rcar-pci-ep.yaml | 1 +
.../dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 5 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 97 ++++++++++++++++++-
drivers/misc/pci_endpoint_test.c | 2 +
4 files changed, 104 insertions(+), 1 deletion(-)

--
2.17.1


[ANNOUNCE] v4.19.152-cip37-rt16

Pavel Machek
 

Hi!

New realtime trees should be available at kernel.org.

I'm doing release at unusual time because the last one had problems
booting on Renesas boards. This one should work ok.

Trees are available at

https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/log/?h=linux-4.19.y-cip-rt
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/log/?h=linux-4.19.y-cip-rt-rebase

And their content should be identical.

Best regards,
Pavel

--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 30 October 2020 10:26
To: Pavel Machek <pavel@denx.de>
Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Hi!

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Series looks okay to me, it is currently being tested. I can
apply/push it if there are no other comments.
Thanks for patches, I pushed out the series.
Thank you.

Cheers,
Prabhakar


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Lad Prabhakar
 

Hi Nobuhiro,

-----Original Message-----
From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
Sent: 30 October 2020 10:58
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; pavel@denx.de
Cc: cip-dev@lists.cip-project.org; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Prabhakar,

-----Original Message-----
From: Prabhakar Mahadev Lad [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Thursday, October 29, 2020 12:36 AM
To: Pavel Machek <pavel@denx.de>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fcip-
dev%2F&amp;data=04%7C01%7Cprabhakar.mahadev-
lad.rj%40bp.renesas.com%7C55e2a70e90c54aed478908d87cc2ab6c%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637396522
837081719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;
sdata=P4d9zKypm%2B0kGpmD32bPiC2W6SXLX5Fp%2Fm99bwzb6Y8%3D&amp;reserved=0
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled
as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.
OK.


Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)
Thank you for attaching the test results.
I will apply and push this series.
Thank you.

Cheers,
Prabhakar


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Nobuhiro Iwamatsu
 

Hi Prabhakar,

-----Original Message-----
From: Prabhakar Mahadev Lad [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Thursday, October 29, 2020 12:36 AM
To: Pavel Machek <pavel@denx.de>
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled
as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.
OK.


Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)
Thank you for attaching the test results.
I will apply and push this series.


Cheers,
Prabhakar
Best regards,
Nobuhiro


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Pavel Machek
 

Hi!

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Series looks okay to me, it is currently being tested. I can
apply/push it if there are no other comments.
Thanks for patches, I pushed out the series.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Pavel Machek
 

Hi!

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Series looks okay to me, it is currently being tested. I can
apply/push it if there are no other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Lad Prabhakar
 

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Lad Prabhakar via lists.cip-project.org
Sent: 29 October 2020 11:46
To: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [cip-dev] [PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Hi All,

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.
Missed to mention all the patches have been cherry picked from v5.10-rc1.

Cheers,
Prabhakar


Fabrizio Castro (2):
dt-bindings: ata: sata_rcar: Add r8a774b1 support
arm64: dts: renesas: r8a774b1: Add SATA controller node

Geert Uytterhoeven (1):
ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar (1):
arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata

Documentation/devicetree/bindings/ata/sata_rcar.txt | 7 +++++--
.../boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++++
drivers/ata/sata_rcar.c | 2 +-
4 files changed, 22 insertions(+), 3 deletions(-)

--
2.17.1


[PATCH 4.19.y-cip 4/4] ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar
 

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit df9c590986fdb6db9d5636d6cd93bc919c01b451 upstream.

Before commit 9495b7e92f716ab2 ("driver core: platform: Initialize
dma_parms for platform devices"), the R-Car SATA device didn't have DMA
parameters. Hence the DMA boundary mask supplied by its driver was
silently ignored, as __scsi_init_queue() doesn't check the return value
of dma_set_seg_boundary(), and the default value of 0xffffffff was used.

Now the device has gained DMA parameters, the driver-supplied value is
used, and the following warning is printed on Salvator-XS:

DMA-API: sata_rcar ee300000.sata: mapping sg segment across boundary [start=0x00000000ffffe000] [end=0x00000000ffffefff] [boundary=0x000000001ffffffe]
WARNING: CPU: 5 PID: 38 at kernel/dma/debug.c:1233 debug_dma_map_sg+0x298/0x300

(the range of start/end values depend on whether IOMMU support is
enabled or not)

The issue here is that SATA_RCAR_DMA_BOUNDARY doesn't have bit 0 set, so
any typical end value, which is odd, will trigger the check.

Fix this by increasing the DMA boundary value by 1.

This also fixes the following WRITE DMA EXT timeout issue:

# dd if=/dev/urandom of=/mnt/de1/file1-1024M bs=1M count=1024
ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
ata1.00: failed command: WRITE DMA EXT
ata1.00: cmd 35/00:00:00:e6:0c/00:0a:00:00:00/e0 tag 0 dma 1310720 out
res 40/00:01:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
ata1.00: status: { DRDY }

as seen by Shimoda-san since commit 429120f3df2dba2b ("block: fix
splitting segments on boundary masks").

Fixes: 8bfbeed58665dbbf ("sata_rcar: correct 'sata_rcar_sht'")
Fixes: 9495b7e92f716ab2 ("driver core: platform: Initialize dma_parms for platform devices")
Fixes: 429120f3df2dba2b ("block: fix splitting segments on boundary masks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/ata/sata_rcar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 8323f88d17a5..4dcdf8ee0055 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -124,7 +124,7 @@
/* Descriptor table word 0 bit (when DTA32M = 1) */
#define SATA_RCAR_DTEND BIT(0)

-#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
+#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL

/* Gen2 Physical Layer Control Registers */
#define RCAR_GEN2_PHY_CTL1_REG 0x1704
--
2.17.1


[PATCH 4.19.y-cip 3/4] arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata

Lad Prabhakar
 

commit e7cc614be7886b464a429f83162171128c205b2e upstream.

Enable sata interface on HiHope RZ/G2N board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200810171239.30401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
index a3edd55113df..60d7c8adea02 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts
@@ -14,3 +14,8 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+&sata {
+ status = "okay";
+};
--
2.17.1


[PATCH 4.19.y-cip 2/4] arm64: dts: renesas: r8a774b1: Add SATA controller node

Lad Prabhakar
 

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 1510faee309010194ebb6ad3068cc9c0f7bc761b upstream.

Add the SATA controller node to the RZ/G2N SoC specific
dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1571761279-17347-3-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 62d011107cc5..11cc0f274ef3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1902,6 +1902,17 @@
status = "disabled";
};

+ sata: sata@ee300000 {
+ compatible = "renesas,sata-r8a774b1",
+ "renesas,rcar-gen3-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1


[PATCH 4.19.y-cip 1/4] dt-bindings: ata: sata_rcar: Add r8a774b1 support

Lad Prabhakar
 

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit b00e14c536574fb3e45aa0cf899e67fc3ac51d06 upstream.

Document SATA support for the RZ/G2N, no driver change required.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/ata/sata_rcar.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt
index 4268e17d2411..a2fbdc91570d 100644
--- a/Documentation/devicetree/bindings/ata/sata_rcar.txt
+++ b/Documentation/devicetree/bindings/ata/sata_rcar.txt
@@ -2,6 +2,7 @@

Required properties:
- compatible : should contain one or more of the following:
+ - "renesas,sata-r8a774b1" for RZ/G2N
- "renesas,sata-r8a7779" for R-Car H1
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
@@ -9,8 +10,10 @@ Required properties:
- "renesas,sata-r8a7793" for R-Car M2-N
- "renesas,sata-r8a7795" for R-Car H3
- "renesas,sata-r8a77965" for R-Car M3-N
- - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
- - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
+ - "renesas,rcar-gen2-sata" for a generic R-Car Gen2
+ compatible device
+ - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
+ RZ/G2 compatible device
- "renesas,rcar-sata" is deprecated

When compatible with the generic version nodes
--
2.17.1


[PATCH 4.19.y-cip 0/4] Add SATA support to RZ/G2N

Lad Prabhakar
 

Hi All,

This patch series adds SATA support to RZ/G2N SoC and enables
sata node in Hihope RZ/G2N board, alongside a fix to sata driver.

Cheers,
Prabhakar

Fabrizio Castro (2):
dt-bindings: ata: sata_rcar: Add r8a774b1 support
arm64: dts: renesas: r8a774b1: Add SATA controller node

Geert Uytterhoeven (1):
ata: sata_rcar: Fix DMA boundary mask

Lad Prabhakar (1):
arm64: dts: renesas: r8a774b1-hihope-rzg2n-ex: Enable sata

Documentation/devicetree/bindings/ata/sata_rcar.txt | 7 +++++--
.../boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++++
drivers/ata/sata_rcar.c | 2 +-
4 files changed, 22 insertions(+), 3 deletions(-)

--
2.17.1


Re: cip-kernel-sec Updates for Last Week of October

masashi.kudo@cybertrust.co.jp <masashi.kudo@...>
 

Hi, Chen-Yu san,

Thanks for your report! This is very helpful.

Could you add the backporting status for 4.4 and 4.19 stable kernels?
We may want to discuss the necessity of the backporting for them.

Best regards,
--
M. Kudo

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of
Chen-Yu Tsai (Moxa)
Sent: Thursday, October 29, 2020 11:42 AM
To: cip-dev@lists.cip-project.org
Cc: Pavel Machek <pavel@denx.de>; Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@toshiba.co.jp>
Subject: [cip-dev] cip-kernel-sec Updates for Last Week of October

Hi everyone,

Since there's no CIP weekly meeting this week, I'm sharing the details on the
mailing list. If people prefer this format, I can also do this in the future. This could
make up for the merge request which summarized the information.

Here's this week's update:

New CVEs:
- CVE-2019-0146 [net/i40e] - likely fixed
- CVE-2020-27673 [xen/dom0] - fixed in mainline
- CVE-2020-27675 [xen/dom0] - fixed in mainline

Old CVEs now fixed:
- CVE-2020-14351 [perf] - fixed in mainline
- CVE-2020-27152 [KVM] - fixed in mainline

So we have yet another Intel i40e CVE that has a nearly useless description.

For the rest, they are all fixed in v5.10-rc1.

- Fixes for CVE-2020-14351 and CVE-2020-27152 have been queued
up for v5.8 and v5.9.

- Fix for CVE-2020-27675 has been queued up for v5.9

- Fix for CVE-2020-27673 has not been backported yet.


Regards
ChenYu
Moxa


cip-kernel-sec Updates for Last Week of October

Chen-Yu Tsai (Moxa) <wens@...>
 

Hi everyone,

Since there's no CIP weekly meeting this week, I'm sharing the details
on the mailing list. If people prefer this format, I can also do this
in the future. This could make up for the merge request which summarized
the information.

Here's this week's update:

New CVEs:
- CVE-2019-0146 [net/i40e] - likely fixed
- CVE-2020-27673 [xen/dom0] - fixed in mainline
- CVE-2020-27675 [xen/dom0] - fixed in mainline

Old CVEs now fixed:
- CVE-2020-14351 [perf] - fixed in mainline
- CVE-2020-27152 [KVM] - fixed in mainline

So we have yet another Intel i40e CVE that has a nearly useless
description.

For the rest, they are all fixed in v5.10-rc1.

- Fixes for CVE-2020-14351 and CVE-2020-27152 have been queued
up for v5.8 and v5.9.

- Fix for CVE-2020-27675 has been queued up for v5.9

- Fix for CVE-2020-27673 has not been backported yet.


Regards
ChenYu
Moxa


No IRC meeting today

masashi.kudo@cybertrust.co.jp <masashi.kudo@...>
 

Hi,

It is just a reminder.
As we discussed at the IRC meeting last week, there is no IRC meeting this week.

See you next week,
--
M. Kudo


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 28 October 2020 15:27
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.
It's the same controller which works as a host and endpoint (PCIe EP). By default on the boards controller is enabled as host and not EP as a result status is set to disabled. So during testing host is disabled and EP is enabled.

Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).
Attached are the results for G2M as PCIe host and G2N as PCIe EP tested on CIP kernel.

So on the host pcietest read/write/copy commands are tested (also lspci output)

Cheers,
Prabhakar

Best regards,
Pavel


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Pavel Machek
 

Hi!

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both
Series looks good to me.

arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
I see that the nodes are stil marked as "disabled"... I guess
devboards are not plugged into into PCIe hosts for the testing.

Anyway, it would be good to know if the merged -cip code was tested
and what was the result :-).

Best regards,
Pavel


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Leaving Codethink and CIP

Ben Hutchings <ben.hutchings@...>
 

I will be leaving Codethink next month, and will no longer be working
directly on CIP. (With my Debian hat on, I may still submit merge
requests to the cip-kernel-sec repository.) My last working day here
will be 11 November.

I want to thank everyone who's worked to make super-long-term Linux
kernel maintenance possible. CIP has a great kernel team now and I'm
confident that you'll carry on doing a fine job without me.

Ben.

--
Ben Hutchings, Software Developer Codethink Ltd
https://www.codethink.co.uk/ Dale House, 35 Dale Street
Manchester, M1 2HF, United Kingdom


Re: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Nobuhiro Iwamatsu
 

Hi,

Thanks for your work.

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Wednesday, October 28, 2020 1:56 AM
To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 4.19.y-cip 0/5] Add PCIe EP nodes to RZ/G2{EMN}

Hi All,

These patches are part of RFC series [1] ({43-46,48}/50),
these were dropped earlier as they weren't part of -rc release
at the time of posting now that patches have landed in v5.10-rc1
I am resending them with non-RFC tag.

[1] https://patchwork.kernel.org/project/cip-dev/
list/?series=363279&state=%2A&archive=both

Cheers,
Prabhakar

Lad Prabhakar (5):
dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
arm64: dts: renesas: r8a774c0: Add PCIe EP node
arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
controllers
I have reviewed this patch series. There seems to be no problem.
I will apply this if there is no other opinion.

Best regards,
Nobuhiro


.../devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++-
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 ++++++++++
drivers/misc/pci_endpoint_test.c | 7 +++-
5 files changed, 105 insertions(+), 4 deletions(-)

--
2.17.1

1361 - 1380 of 7061