Date   

[Solved] RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Nobuhiro Iwamatsu
Sent: Tuesday, March 16, 2021 3:54 PM
To: cip-dev@lists.cip-project.org
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org
[mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo Koguchi
Sent: Tuesday, March 16, 2021 2:54 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};t
};
```
I am going to look into the difference.
I confirmed that "n25q512a" in the node name and the compatible string are the only difference.
Interestingly, if I used compatible = "n25q512a" instead of compatible
= "s25fl128s1" or "s25fl128s", which is the current setting for
linux-4.19.177-cip, the kernel prints the following message and is able to detect spi-nor flash as expected.

[ 2.701294] spi-nor spi0.0: found s25fl128s1, expected n25q512a
[ 2.711093] spi-nor spi0.0: s25fl128s1 (16384 Kbytes)

Probably the detect mechanism has been changed by the commit.
Apparently setting compatible = "n25q512a" for my board does not make
sense. I'd like to find out why compatible = "s25fl128s1" does not work.
Probably because they are not registered as compatible strings in the driver. They seem to be used as chip names rather
than compatible strings.
Currently, the implementation is to specify "jedec,spi-nor" for the compatible string.
Adding "jedec,spi-nor" to the compatible string has solved the issue.
Now I can confirm that "[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework" is good, and cadence-quadspi is working fine on cyclone V with linux-5.10.y

Thanks!

Takuo Koguchi

Best regards,
Nobuhiro

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Monday, March 15, 2021 2:31 PM
To: cip-dev@lists.cip-project.org
Subject: RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@lists.cip-project.org
<cip-dev@lists.cip-project.org> On Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@lists.cip-project.org
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@lists.cip-project.org
[mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo
Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to
drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error
messages, but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHEr
nB9s
lV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WA
FTDu
H_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy
-gu1
VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_
ousV
eVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-c
ip.g
it%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to
drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to
drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194
Groebenzell, Germany



Re: Is cadence-quadspi working on cyclone V?

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo Koguchi
Sent: Tuesday, March 16, 2021 2:54 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};t
};
```
I am going to look into the difference.
I confirmed that "n25q512a" in the node name and the compatible string are the only difference.
Interestingly, if I used compatible = "n25q512a" instead of compatible = "s25fl128s1" or "s25fl128s",
which is the current setting for linux-4.19.177-cip,
the kernel prints the following message and is able to detect spi-nor flash as expected.

[ 2.701294] spi-nor spi0.0: found s25fl128s1, expected n25q512a
[ 2.711093] spi-nor spi0.0: s25fl128s1 (16384 Kbytes)

Probably the detect mechanism has been changed by the commit.
Apparently setting compatible = "n25q512a" for my board does not make sense. I'd like to find out why
compatible = "s25fl128s1" does not work.
Probably because they are not registered as compatible strings in the driver. They seem to be used as
chip names rather than compatible strings.
Currently, the implementation is to specify "jedec,spi-nor" for the compatible string.

Best regards,
Nobuhiro

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Monday, March 15, 2021 2:31 PM
To: cip-dev@lists.cip-project.org
Subject: RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@lists.cip-project.org
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@lists.cip-project.org
[mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages,
but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHErnB9s
lV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WAFTDu
H_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy-gu1
VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_ousV
eVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-cip.g
it%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
Germany



Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Iwamatsu-san,

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};t
};
```
I am going to look into the difference.
I confirmed that "n25q512a" in the node name and the compatible string are the only difference.
Interestingly, if I used compatible = "n25q512a" instead of compatible = "s25fl128s1" or "s25fl128s",
which is the current setting for linux-4.19.177-cip,
the kernel prints the following message and is able to detect spi-nor flash as expected.

[ 2.701294] spi-nor spi0.0: found s25fl128s1, expected n25q512a
[ 2.711093] spi-nor spi0.0: s25fl128s1 (16384 Kbytes)

Probably the detect mechanism has been changed by the commit.
Apparently setting compatible = "n25q512a" for my board does not make sense. I'd like to find out why
compatible = "s25fl128s1" does not work.

Regards,

Takuo Koguchi

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Monday, March 15, 2021 2:31 PM
To: cip-dev@lists.cip-project.org
Subject: RE: [cip-dev] Is cadence-quadspi working on cyclone V?

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@lists.cip-project.org
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@lists.cip-project.org
[mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages,
but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHErnB9s
lV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WAFTDu
H_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy-gu1
VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_ousV
eVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-cip.g
it%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code.
But it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
Germany



Re: CIP kernel release delayed

Chris Paterson
 

Hello,

From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
Behalf Of Nobuhiro Iwamatsu via lists.cip-project.org
Sent: 15 March 2021 21:08

Hello,

The kernel team are planning to release new CIP kernel last weekend, but
we are currently having problems[0]
with the LAVA lab and can't run test it on some reference boards. Therefore,
the release will be delayed.
As soon as LAVA lab is restored, we will test and release it.
Sorry about this!
lab-cip-renesas has been having network issues. We installed a new router today but it didn't fix our woes.
Discussions with the ISP are ongoing.

Kind regards, Chris


Sorry for contacting you late.

Best regards,
Nobuhiro

[0]:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flava.c
iplatform.org%2Fscheduler%2Falldevices%2Factive&amp;data=04%7C01%7C
chris.paterson2%40renesas.com%7Caa69b8b4019844448bc708d8e7f67837%7
C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637514393074524293%
7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
JBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=nWs9tSorSmUA3j9A
bhIUc8hk08fDdiNfKNIUNrNlH74%3D&amp;reserved=0


CIP kernel release delayed

Nobuhiro Iwamatsu
 

Hello,

The kernel team are planning to release new CIP kernel last weekend, but we are currently having problems[0]
with the LAVA lab and can't run test it on some reference boards. Therefore, the release will be delayed.
As soon as LAVA lab is restored, we will test and release it.

Sorry for contacting you late.

Best regards,
Nobuhiro

[0]: https://lava.ciplatform.org/scheduler/alldevices/active


Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Iwamatsu-san,

Thank you for the information.
It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```
I am going to look into the difference.

Takuo Koguchi

-----Original Message-----
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Nobuhiro Iwamatsu
Sent: Monday, March 15, 2021 2:25 PM
To: cip-dev@lists.cip-project.org
Subject: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@lists.cip-project.org
[mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But
it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result; # first bad commit:
[a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert
cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476
+++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages, but
it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.

https://secure-web.cisco.com/1ChOMrKnSBR5QZeejvrNs3Pf4x8__M_QVUHErnB9slV-TAWP3NUwe0LEzsirvM7rr-Oqv
RKrgxgI3iQo5ITdUehFyDppd2GljkEzx7izv16pERniX0DeDmzwE5h9pUYqtIxO3WAFTDuH_EG-RNhNFqK4LQakZ90sESF6
DMvs_jovN55Xj5u9kNOC_ew76pLtAMAOdN3BZSV_fR_n6tcWlhvqJ6OlUEfrpz9xvy-gu1VHrgcgj1BICaBid9bVUza1-T7rBc
I2EjECtd0qCMcsvLYZPxvzfZ9-Hu6rFlaCQ0ruhxZVfHuVWEB37eQmm0HLHYJG2_R_ousVeVDk8bJa2iA/https%3A%2F%2
Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fcip%2Flinux-cip.git%2Ftree%2Farch%2Farm%2Fboot%2Fd
ts%2Fsocfpga_cyclone5_sodia.dts%3Fh%3Dlinux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But
it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But
it touches Kconfig bits; can you check that
CONFIG_SPI_CADENCE_QUADSPI is enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
Germany



Re: Is cadence-quadspi working on cyclone V?

Nobuhiro Iwamatsu
 

Hi Koguchi-san,

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Takuo Koguchi
Sent: Monday, March 15, 2021 1:33 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result;
# first bad commit: [a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert cadence-quadspi to use spi-mem
framework

It contains significant amount of changes;

cadence-quadspi.c | 476 +++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages, but it does not detect NOR flash on a custom cyclone
V board.

Any information will be appreciated.
I checked on a Sodia board with the same SoC.
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/tree/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts?h=linux-5.10.y-cip

It recognizes NOR flash in 5.10.y. How about checking DTS?
Sodia board uses n25q512a and has the following DT:
```
&qspi {
status = "okay";

flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
reg = <0>;
spi-max-frequency = <100000000>;

m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
```

Thanks,

Takuo Koguchi
Best regards,
Nobuhiro


-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi Pavel,

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.
I redo the bisect and get the following result;
# first bad commit: [a314f6367787ee1d767df9a2120f17e4511144d0] mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework

It contains significant amount of changes;

cadence-quadspi.c | 476 +++++++++++++++++++++---------------------------------
1 file changed, 191 insertions(+), 285 deletions(-)

With this change, cpspi_probe return 0 without any error messages, but it does not detect NOR flash on a custom cyclone V board.

Any information will be appreciated.

Thanks,

Takuo Koguchi

-----Original Message-----
From: 小口琢夫 / KOGUCHI,TAKUO
Sent: Sunday, March 14, 2021 4:37 PM
To: cip-dev@lists.cip-project.org
Subject: Re: [!]Re: [cip-dev] Is cadence-quadspi working on cyclone V?

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



Re: master branch at git.kernel.org/...cip

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Pavel Machek
Sent: Thursday, March 11, 2021 9:43 PM
To: Chris.Paterson2@renesas.com; cip-dev@lists.cip-project.org
Subject: [cip-dev] master branch at git.kernel.org/...cip

Hi!

Chris pointed out our master branch at git.kernel.org is rather old:

https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/refs/heads

master CIP: Bump version suffix to -cip28 after Renesas patches Ben Hutchings 2 years


Master branch is really not too applicable for our workflow. Yes, 2
years old version of 4.4 looks out of place.

I see these options:

1) leave it alone. (+) It is quite obvious development is not
happening there (-) It looks strange.

2) delete it. (-) I'm not sure that is possible or what problems it
might cause.

3) update it to Linus' 5.12-rc1 and keep it updated. (-) Extra work to
keep it updated, (-) we don't really do anything with mainline commits
newer than 5.10

4) update it to Linus' 5.10, and only touch it when the linux-5.21-cip
is branched out.

Any other ideas?

My preference would be (1) and (4).
I want to choose 1 or 3.
We have multiple release branches, so setting the branch that manages a particular version to
the master branch can be a bit confusing. How about managing a branch similar to LTS tree?

Best regards,
Nobuhiro


Re: Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi Pavel,
Thank you for the response.

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?
I have no local changes to those files.
Maybe I lost CONFIG_SPI_CADENCE_QUADSPI accidentally while bisecting.
I will try bisect and post the result again.

Regards,

Takuo Koguchi

2021/03/13 8:07、Pavel Machek <pavel@denx.de>のメール:

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany



Re: Is cadence-quadspi working on cyclone V?

Pavel Machek
 

Hi!

Git bisect has told me the first bad commit is
31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/
That's strange.

Does this change requires device tree modification?
Any suggestions or comments would be appreciated.
...because that particular change does not change any C code. But it
touches Kconfig bits; can you check that CONFIG_SPI_CADENCE_QUADSPI is
enabled in the "bad" configuration?

Do you have any local changes in
drivers/mtd/spi-nor/controllers/cadence-quadspi.c or
drivers/spi/spi-cadence-quadspi.c ?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Is cadence-quadspi working on cyclone V?

Takuo Koguchi
 

Hi CIP developers,

 

Can anyone confirm that spi-cadence-quadspi works fine with SPI-NOR on cyclone V?

I recently moved to 5.10.y-cip from 4.19.y-cip, then my custom board with cyclone V failed to detect SPI-NOR

 

Git bisect has told me the first bad commit is

31fb632b5d43 spi: Move cadence-quadspi driver to drivers/spi/

 

Does this change requires device tree modification?

Any suggestions or comments would be appreciated.

 

Takuo Koguchi

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V


master branch at git.kernel.org/...cip

Pavel Machek
 

Hi!

Chris pointed out our master branch at git.kernel.org is rather old:

https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/refs/heads

master CIP: Bump version suffix to -cip28 after Renesas patches Ben Hutchings 2 years


Master branch is really not too applicable for our workflow. Yes, 2
years old version of 4.4 looks out of place.

I see these options:

1) leave it alone. (+) It is quite obvious development is not
happening there (-) It looks strange.

2) delete it. (-) I'm not sure that is possible or what problems it
might cause.

3) update it to Linus' 5.12-rc1 and keep it updated. (-) Extra work to
keep it updated, (-) we don't really do anything with mainline commits
newer than 5.10

4) update it to Linus' 5.10, and only touch it when the linux-5.21-cip
is branched out.

Any other ideas?

My preference would be (1) and (4).

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


4.4 futex: Change locking rules

Pavel Machek
 

Hi!

There was some discussion about futexes in 4.4 on irc.

https://lore.kernel.org/stable/20210309030605.3295183-2-zhengyejian1@huawei.com/

I don't believe we need to do anything there. Peter Zijlstra is
re-doing locking for futexes, which will have benefits for future
realtime releases. But we have separate patches for 4.4-rt, so we
should be fine.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Cip-kernel-sec Updates for Week of 2021-03-11

Chen-Yu Tsai (Moxa) <wens@...>
 

Hi everyone,

Seven new CVEs this week:
- CVE-2021-20265 [af_unix: memory leak] - fixed
- CVE-2021-20268 [ebpf: signed type overflow] - fixed
- CVE-2021-27363 [iscsi: iscsi_host_get_param() allows sysfs params
larger than 4k] - fixed
- CVE-2021-27364 [iscsi: iscsi_if_recv_msg allows non-root user] - fixed
- CVE-2021-27365 [iscsi: heap buffer overflow] - fixed
- CVE-2021-28038 [xen: netback: fails to honor errors] - fixed
- CVE-2021-28039 [xen: incorrect foreign pages mapping under special
config] - fixed

All fixes have been backported to all relevant stable kernels.

Also, 4.9.y specific follow-up patch for CVE-2020-29368 was merged in 4.9.259.


Regards
ChenYu


Re: CIP IRC weekly meeting today

Nobuhiro Iwamatsu
 

Hi all,

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of
masashi.kudo@cybertrust.co.jp
Sent: Thursday, March 11, 2021 9:23 AM
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] CIP IRC weekly meeting today

Hi all,

Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.
Sorry, I can not participate today's IRC meeting for personal reason.


*Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting from the first week of Apr. according
to TSC meeting*
https://www.timeanddate.com/worldclock/meetingdetails.html?year=2021&month=3&day=11&hour=9&min=0&sec=0&p1=224&p2=
179&p3=136&p4=37&p5=241&p6=248

USWest USEast UK DE TW JP
01:00 04:00 9:00 10:00 17:00 18:00

Channel:
* irc:chat.freenode.net:6667/cip

Last meeting minutes:
https://irclogs.baserock.org/meetings/cip/2021/03/cip.2021-03-04-09.00.log.html

* Action item
1. Combine root filesystem with kselftest binary - iwamatsu
No update.

2. Do some experiment to lower burdens on CI - patersonc

* Kernel maintenance updates
I reviewed 4.4.260, 5.10.21 and 5.10.22.

* Kernel testing
* CIP Security
* AOB

The meeting will take 30 min, although it can be extended to an hour if it makes sense and those involved in the topics
can stay. Otherwise, the topic will be taken offline or in the next meeting.

Best regards,
Best regards.
Nobuhiro

--
M. Kudo
Cybertrust Japan Co., Ltd.


CIP IRC weekly meeting today

masashi.kudo@cybertrust.co.jp
 

Hi all,

Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.

*Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting from the first week of Apr. according to TSC meeting*
https://www.timeanddate.com/worldclock/meetingdetails.html?year=2021&month=3&day=11&hour=9&min=0&sec=0&p1=224&p2=179&p3=136&p4=37&p5=241&p6=248

USWest USEast UK DE TW JP
01:00 04:00 9:00 10:00 17:00 18:00

Channel:
* irc:chat.freenode.net:6667/cip

Last meeting minutes:
https://irclogs.baserock.org/meetings/cip/2021/03/cip.2021-03-04-09.00.log.html

* Action item
1. Combine root filesystem with kselftest binary - iwamatsu
2. Do some experiment to lower burdens on CI - patersonc

* Kernel maintenance updates
* Kernel testing
* CIP Security
* AOB

The meeting will take 30 min, although it can be extended to an hour if it makes sense and those involved in the topics can stay. Otherwise, the topic will be taken offline or in the next meeting.

Best regards,
--
M. Kudo
Cybertrust Japan Co., Ltd.


Re: [PATCH 4.19.y-cip 00/40] Renesas RZ/G2{E,H,M,N} add VIN, CSI2 support

Chris Paterson
 

Hello Pavel, Iwamatsu-san,

From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
Behalf Of Nobuhiro Iwamatsu via lists.cip-project.org
Sent: 10 March 2021 08:08

Hi,

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Wednesday, March 10, 2021 1:36 AM
To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋
□SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 4.19.y-cip 00/40] Renesas RZ/G2{E,H,M,N} add VIN, CSI2
support

Hi All,

This patch series does the following:
* Drops unneeded regulator setup for OV5645 sensor
* Adds driver for IMX219 sensor
* Updates v4l2-async to accept endpoints for fwnode matching
* Various fixes for R-Car VIN driver
* Support to capture RAW format to VIN driver
* Support for RZ/G2{H,M,N,E} SoC's in VIN/CSI2 driver
* DTS changes for HiHope RZ/G2{H,M,N} and SI Linux RZ/G2E to
enable VIN, CSI2 modules and OV5645, IMX219 sensors.
I reviewed this series, I didn't see any major problems.
As Paval points out, the Renesas lab is now stopped.
If this recovers and the target hardware test is okay, I would apply this.
Sorry about the lab-cip-renesas issues. The lab will probably be offline until next week.
I'm happy for this series to be delayed until it's tested if that's what you'd prefer.

Kind regards, Chris

Cheers,
Prabhakar
Best regards,
Nobuhiro



Andrey Konovalov (1):
media: dt-bindings: media: i2c: Add IMX219 CMOS sensor binding

Biju Das (10):
media: dt-bindings: media: rcar_vin: Add r8a774a1 support
media: rcar-vin: Enable support for r8a774a1
media: dt-bindings: media: rcar-csi2: Add r8a774a1 support
media: rcar-csi2: Enable support for r8a774a1
arm64: dts: renesas: r8a774a1: Add VIN and CSI-2 nodes
media: dt-bindings: rcar-vin: Add R8A774B1 support
media: rcar-vin: Enable support for R8A774B1
media: dt-bindings: rcar-csi2: Add R8A774B1 support
media: rcar-csi2: Enable support for R8A774B1
arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support

Dafna Hirschfeld (1):
media: i2c: imx219: Fix a bug in imx219_enum_frame_size

Dave Stevenson (1):
media: i2c: Add driver for Sony IMX219 sensor

Fabio Estevam (1):
media: ov5645: Remove unneeded regulator_set_voltage()

Hans Verkuil (2):
media: i2c: imx219: Selection compliance fixes
media: i2c: imx219: take lock in imx219_enum_mbus_code/frame_size

Jacopo Mondi (1):
media: i2c: imx219: Implement get_selection

Lad Prabhakar (16):
media: rcar-vin: Invalidate pipeline if conversion is not possible on
input formats
media: rcar-vin: Add support for MEDIA_BUS_FMT_SRGGB8_1X8 format
media: rcar-csi2: Add support for MEDIA_BUS_FMT_SRGGB8_1X8 format
media: i2c: imx219: Fix power sequence
media: i2c: imx219: Add support for RAW8 bit bayer format
media: i2c: imx219: Add support for cropped 640x480 resolution
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION
MIPI Adapter V2.1
media: dt-bindings: media: renesas,vin: Add R8A774E1 support
media: rcar-vin: Enable support for R8A774E1
media: dt-bindings: media: renesas,csi2: Add R8A774E1 support
media: rcar-csi2: Enable support for R8A774E1
arm64: dts: renesas: r8a774e1: Add VIN and CSI-2 nodes
arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro
for each sensor
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2H
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2M
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2N

Laurent Pinchart (4):
media: device property: Add a function to test is a fwnode is a graph
endpoint
media: v4l2-async: Accept endpoints and devices for fwnode matching
media: v4l2-async: Pass notifier pointer to match functions
media: v4l2-async: Log message in case of heterogeneous fwnode match

Niklas Söderlund (2):
media: rcar-vin: fix wrong return value in rvin_set_channel_routing()
media: rcar-csi2: Update V3M and E3 start procedure

Sakari Ailus (1):
media: v4l: ctrl: Provide unlocked variant of v4l2_ctrl_grab

.../devicetree/bindings/media/i2c/imx219.yaml | 114 ++
.../devicetree/bindings/media/rcar_vin.txt | 3 +
.../bindings/media/renesas,rcar-csi2.txt | 3 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/renesas/Makefile | 10 +-
.../aistarvision-mipi-adapter-2.1.dtsi | 96 +
...rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 ++
.../r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 +
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 367 ++++
.../r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts | 16 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 366 ++++
.../dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 73 +
.../r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 334 ++++
drivers/media/i2c/Kconfig | 11 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/imx219.c | 1582 +++++++++++++++++
drivers/media/i2c/ov5645.c | 28 -
drivers/media/platform/rcar-vin/rcar-core.c | 49 +
drivers/media/platform/rcar-vin/rcar-csi2.c | 23 +-
drivers/media/platform/rcar-vin/rcar-dma.c | 17 +-
drivers/media/platform/rcar-vin/rcar-v4l2.c | 4 +
drivers/media/v4l2-core/v4l2-async.c | 83 +-
drivers/media/v4l2-core/v4l2-ctrls.c | 8 +-
include/linux/property.h | 5 +
include/media/v4l2-ctrls.h | 26 +-
26 files changed, 3330 insertions(+), 51 deletions(-)
create mode 100644
Documentation/devicetree/bindings/media/i2c/imx219.yaml
create mode 100644 arch/arm64/boot/dts/renesas/aistarvision-mipi-
adapter-2.1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/hihope-rzg2-ex-
aistarvision-mipi-adapter-2.1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-
rzg2m-ex-mipi-2.1.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-hihope-
rzg2n-ex-mipi-2.1.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-
2.1.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-
rzg2h-ex-mipi-2.1.dts
create mode 100644 drivers/media/i2c/imx219.c

--
2.17.1


Re: [PATCH 4.19.y-cip 12/40] media: dt-bindings: media: i2c: Add IMX219 CMOS sensor binding

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 10 March 2021 09:39
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Pavel Machek <pavel@denx.de>; cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip 12/40] media: dt-bindings: media: i2c: Add IMX219 CMOS sensor binding

Hi!

+description: |-
+ The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
I assume it is 0.25 inch sensor? 1/4 inch or 0.25 inch would be
understandable, but 1/4.0 is kind of strange.
Agree with you here, but looking at the document [1] its referred the same way "1/4.0".

[1] http://www.opensourceinstruments.com/Electronics/Data/IMX219PQ.pdf
It is refered as "Type 1/4.0" and I'm not really sure what it means.

1/4 inch is 6.35mm, but document states it is 4.6mm.

https://www.photoreview.com.au/tips/buying/unravelling-sensor-sizes/
Thanks for the pointer.

explains this system, but they use 1/4", not 1/4.0, and it translates
that to 4.5mm.

I guess easiest way is to say it is "4.8mm CMOS active pixel digital
image sensor" and forget about confusing inch values.
Totally agree with you (^^4.5mm).

Cheers,
Prabhakar

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.19.y-cip 00/40] Renesas RZ/G2{E,H,M,N} add VIN, CSI2 support

Lad Prabhakar
 

Hi Pavel, Nobuhiro,

-----Original Message-----
From: nobuhiro1.iwamatsu@toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
Sent: 10 March 2021 08:08
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org;
pavel@denx.de
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [PATCH 4.19.y-cip 00/40] Renesas RZ/G2{E,H,M,N} add VIN, CSI2 support

Hi,

-----Original Message-----
From: Lad Prabhakar [mailto:prabhakar.mahadev-lad.rj@bp.renesas.com]
Sent: Wednesday, March 10, 2021 1:36 AM
To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 4.19.y-cip 00/40] Renesas RZ/G2{E,H,M,N} add VIN, CSI2 support

Hi All,

This patch series does the following:
* Drops unneeded regulator setup for OV5645 sensor
* Adds driver for IMX219 sensor
* Updates v4l2-async to accept endpoints for fwnode matching
* Various fixes for R-Car VIN driver
* Support to capture RAW format to VIN driver
* Support for RZ/G2{H,M,N,E} SoC's in VIN/CSI2 driver
* DTS changes for HiHope RZ/G2{H,M,N} and SI Linux RZ/G2E to
enable VIN, CSI2 modules and OV5645, IMX219 sensors.
I reviewed this series, I didn't see any major problems.
Thank you for the review.

As Paval points out, the Renesas lab is now stopped.
If this recovers and the target hardware test is okay, I would apply this.
I have informed Chris about this.

Cheers,
Prabhakar

Cheers,
Prabhakar
Best regards,
Nobuhiro



Andrey Konovalov (1):
media: dt-bindings: media: i2c: Add IMX219 CMOS sensor binding

Biju Das (10):
media: dt-bindings: media: rcar_vin: Add r8a774a1 support
media: rcar-vin: Enable support for r8a774a1
media: dt-bindings: media: rcar-csi2: Add r8a774a1 support
media: rcar-csi2: Enable support for r8a774a1
arm64: dts: renesas: r8a774a1: Add VIN and CSI-2 nodes
media: dt-bindings: rcar-vin: Add R8A774B1 support
media: rcar-vin: Enable support for R8A774B1
media: dt-bindings: rcar-csi2: Add R8A774B1 support
media: rcar-csi2: Enable support for R8A774B1
arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support

Dafna Hirschfeld (1):
media: i2c: imx219: Fix a bug in imx219_enum_frame_size

Dave Stevenson (1):
media: i2c: Add driver for Sony IMX219 sensor

Fabio Estevam (1):
media: ov5645: Remove unneeded regulator_set_voltage()

Hans Verkuil (2):
media: i2c: imx219: Selection compliance fixes
media: i2c: imx219: take lock in imx219_enum_mbus_code/frame_size

Jacopo Mondi (1):
media: i2c: imx219: Implement get_selection

Lad Prabhakar (16):
media: rcar-vin: Invalidate pipeline if conversion is not possible on
input formats
media: rcar-vin: Add support for MEDIA_BUS_FMT_SRGGB8_1X8 format
media: rcar-csi2: Add support for MEDIA_BUS_FMT_SRGGB8_1X8 format
media: i2c: imx219: Fix power sequence
media: i2c: imx219: Add support for RAW8 bit bayer format
media: i2c: imx219: Add support for cropped 640x480 resolution
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION
MIPI Adapter V2.1
media: dt-bindings: media: renesas,vin: Add R8A774E1 support
media: rcar-vin: Enable support for R8A774E1
media: dt-bindings: media: renesas,csi2: Add R8A774E1 support
media: rcar-csi2: Enable support for R8A774E1
arm64: dts: renesas: r8a774e1: Add VIN and CSI-2 nodes
arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro
for each sensor
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2H
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2M
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2N

Laurent Pinchart (4):
media: device property: Add a function to test is a fwnode is a graph
endpoint
media: v4l2-async: Accept endpoints and devices for fwnode matching
media: v4l2-async: Pass notifier pointer to match functions
media: v4l2-async: Log message in case of heterogeneous fwnode match

Niklas Söderlund (2):
media: rcar-vin: fix wrong return value in rvin_set_channel_routing()
media: rcar-csi2: Update V3M and E3 start procedure

Sakari Ailus (1):
media: v4l: ctrl: Provide unlocked variant of v4l2_ctrl_grab

.../devicetree/bindings/media/i2c/imx219.yaml | 114 ++
.../devicetree/bindings/media/rcar_vin.txt | 3 +
.../bindings/media/renesas,rcar-csi2.txt | 3 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/renesas/Makefile | 10 +-
.../aistarvision-mipi-adapter-2.1.dtsi | 96 +
...rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 ++
.../r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 +
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 367 ++++
.../r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts | 16 +
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 366 ++++
.../dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 73 +
.../r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 334 ++++
drivers/media/i2c/Kconfig | 11 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/imx219.c | 1582 +++++++++++++++++
drivers/media/i2c/ov5645.c | 28 -
drivers/media/platform/rcar-vin/rcar-core.c | 49 +
drivers/media/platform/rcar-vin/rcar-csi2.c | 23 +-
drivers/media/platform/rcar-vin/rcar-dma.c | 17 +-
drivers/media/platform/rcar-vin/rcar-v4l2.c | 4 +
drivers/media/v4l2-core/v4l2-async.c | 83 +-
drivers/media/v4l2-core/v4l2-ctrls.c | 8 +-
include/linux/property.h | 5 +
include/media/v4l2-ctrls.h | 26 +-
26 files changed, 3330 insertions(+), 51 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/i2c/imx219.yaml
create mode 100644 arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
create mode 100644 drivers/media/i2c/imx219.c

--
2.17.1

341 - 360 of 6628