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Re: Patches that need porting from 4.19 to 5.10-cip tree
Pavel Machek
Hi!
Thanks a lot for doing this (and sorry for all the false positivesHere is the list of patches that are in 4.19-cip but not yet inPrabhakar has reviewed your list and has submitted all of the relevant patches in his "Renesas RZ/G2 sync patches from 4.19-cip to 5.10-cip" series [0]. from the script). I went through the list for entries where existing commit was not identified, and this is the result: It looks there's a very little work to do: we need to pull 5.10.18 into our tree and there are 4 patches marked as "not required" we need to somehow deal with. Given that we have them in 4.19 (and they add hardware support and are not really invasive), could I ask for their 5.10 ports? That should be least surprising. (If they are not required in 4.19 there, we we could drop them from there, too.) ,,,23,140 49753c6e27ed35223cdab939c34ff1d85f200765 mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support,Not required ,,,103,827 641132722015595793f56fe31765636ddf7a6999 arm64: Add Renesas R8A774C0 support,Not required ,,,104,828 b6ddebb2cc793ef2fda081fd2ef2439c158caac4 arm64: Add Renesas R8A774A1 support,Not required ,,,107,831 76b8e853948bfaff083afb3dd985eb19f3aab30b dt-bindings: arm: Fix RZ/G2E part number,Not required Best regards, Pavel * Patches that need porting from 4.19-cip (second pass) ** We don't need to do anything, as problem is already solved in 5.10 in different way ,,,31,632 37c7e76a75a0d5906d792628e4747607a963ba24 arm64: dts: renesas: r8a774c0: sort subnodes of the soc node,Already sorted in 5.10 ** We don't need to do anything, patch is already in 5.10 (script did not recognize upstream tag) ,,,91,"815 7caccda8939c381fc316f450daa9307d227a4a67 ARM: dts: socfpga: Rename socfpga_cyclone5_de0_{sockit, nano_soc}",Don’t care ,,,30,627 0ccb93953810660266f7095e0541c6db19920642 staging: m57621-mmc: delete driver from the tree.,Don’t care ** We don't need to do anything, patch is already in 5.10-stable ,,,119,843 fc1e3f5d1d7f77be91f85d7d4ce94ebfe3d8d284 kvm: check tlbs_dirty directly,Don’t care in 5.10.7 ,,,120,844 2c68bb33dad9f3cab171bb64e1766bc5a7e9b7e8 scsi: qla2xxx: Fix crash during driver load on big endian machines,Don’t care in 5.10.4 ** Patch series is already in 5.10.18, we need to pull it to -cip ,,,121,845 98f16e171e2849dba76e2e0346e914452c030dc5 xen-blkback: fix error handling in xen_blkbk_map(),Don’t care upstream: 871997bc9e423f05c7da7c9178e62dde5df2a7f8 ,,,122,"846 f84c00fbd27b043fa42a56eaaa14e293877bc69b xen-scsiback: don't ""handle"" error by BUG()",Don’t care upstream: 7c77474b2d22176d2bfb592ec74e0f2cb71352c9 ,,,123,"847 717faa776ca2163119239ea58bb78c4d732d8a4f xen-netback: don't ""handle"" error by BUG()",Don’t care commit 3194a1746e8aabe86075fd3c5e7cf1f4632d7f16 upstream. ,,,124,"848 a01b49a9bf91a723f541139c063c1ff681ac536a xen-blkback: don't ""handle"" error by BUG()",Don’t care commit 5a264285ed1cd32e26d9de4f3c8c6855e467fd63 upstream. ,,,125,849 271a3984f73c485f4c1b796a61cc5bd3994a0463 xen/arm: don't ignore return errors from set_phys_to_machine,Don’t care commit 36bf1dfb8b266e089afa9b7b984217f17027bf35 upstream. ,,,126,850 e07f06f6bbeed5bf47fed79ac6a57ec62b33304a Xen/gntdev: correct error checking in gntdev_map_grant_pages(),Don’t care commit ebee0eab08594b2bd5db716288a4f1ae5936e9bc upstream. ** Investigate: ,,,23,140 49753c6e27ed35223cdab939c34ff1d85f200765 mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support,Not required ,,,103,827 641132722015595793f56fe31765636ddf7a6999 arm64: Add Renesas R8A774C0 support,Not required ,,,104,828 b6ddebb2cc793ef2fda081fd2ef2439c158caac4 arm64: Add Renesas R8A774A1 support,Not required ,,,107,831 76b8e853948bfaff083afb3dd985eb19f3aab30b dt-bindings: arm: Fix RZ/G2E part number,Not required -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: Patches that need porting from 4.19 to 5.10-cip tree
Pavel Machek
Hi!
Thanks for doing this, let me take a look.*** gpg4o | HINT: Error while checking message with detached signaturePrabhakar has reviewed your list and has submitted all of the relevant patches in his "Renesas RZ/G2 sync patches from 4.19-cip to 5.10-cip" series [0]. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: Patches that need porting from 4.19 to 5.10-cip tree
Chris Paterson
Hello Pavel,
From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> OnPrabhakar has reviewed your list and has submitted all of the relevant patches in his "Renesas RZ/G2 sync patches from 4.19-cip to 5.10-cip" series [0]. Attached is a spreadsheet that summarises his analysis. As you can see there are a lot of patches that are already present in v5.10, and some aren't needed. There are a few patches marked as "Don't care". This is from a Renesas/RZ/G point of view. They should probably still be looked into by someone in CIP. [0] https://patchwork.kernel.org/project/cip-dev/list/?series=504483 Kind regards, Chris
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Re: [PATCH 5.10.y-cip 00/16] Renesas RZ/G2 sync patches from 4.19-cip to 5.10-cip
Nobuhiro Iwamatsu
Hi all,
toggle quoted messageShow quoted text
-----Original Message-----Looks good to me, too. I applied to and pushed. Best regards, Nobuhiro
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Re: Failing -stable-rc tests
Michael Adler
Hi Pavel,
This is one of the common failures:I suspect this is a network issue on the runner node: - upload to AWS S3 failed - upload to the Gitlab storage failed too I'm wondering if this is just a temporary issue (which goes away after waiting for a couple of minutes) of if the network is permanently down on our (ephermal) runner node. I suggest adding some retry error handling logic to `/opt/submit_tests.sh`: if the upload to AWS S3 fails, perform some network health checks, in particular ping/curl some other site like google.com, and try the upload again for a few minutes. I have also upgraded our runners to v14 (although I don't think that will help in this case). Kind Regards, Michael -- Michael Adler Siemens AG T RDA IOT SES-DE Otto-Hahn-Ring 6 81739 München, Deutschland Siemens Aktiengesellschaft: Vorsitzender des Aufsichtsrats: Jim Hagemann Snabe; Vorstand: Roland Busch, Vorsitzender; Klaus Helmrich, Cedrik Neike, Matthias Rebellius, Ralf P. Thomas, Judith Wiese; Sitz der Gesellschaft: Berlin und München, Deutschland; Registergericht: Berlin-Charlottenburg, HRB 12300, München, HRB 6684; WEEE-Reg.-Nr. DE 23691322
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Re: [isar-cip-core][PATCH v2 1/1] swupdate: Add option to use swupdate-handler-roundrobin
Jan Kiszka
On 18.06.21 20:08, Quirin Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@siemens.com>Thanks, applied to next. Jan -- Siemens AG, T RDA IOT Corporate Competence Center Embedded Linux
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Re: Failing -stable-rc tests
Chris Paterson
Hello Pavel,
From: Pavel Machek <pavel@denx.de>This is something we sometimes see in LAVA. It's not 100% reliable in getting the serial connection to the board up and running :( Yea. It's annoying though. Same test, same board: https://lava.ciplatform.org/scheduler/job/302551 Kind regards, Chris
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Re: Failing -stable-rc tests
Pavel Machek
Hi!
I re-tried, and now I got this:From: Pavel Machek <pavel@denx.de>Thanks for sharing the details. https://lava.ciplatform.org/scheduler/job/302528 I'll retry once more, I believe it will go way. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: Failing -stable-rc tests
Chris Paterson
Hi Pavel,
From: Pavel Machek <pavel@denx.de>Thanks for sharing the details. We'll take a look. Kind regards, Chris
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Re: [PATCH 5.10.y-cip 00/16] Renesas RZ/G2 sync patches from 4.19-cip to 5.10-cip
Pavel Machek
Hi!
This patch series sync's patches from 4.19-cip to 5.10-cip.Looks good to me. I'll apply it if there are no other comments. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Failing -stable-rc tests
Pavel Machek
Hi!
This is one of the common failures: https://gitlab.com/cip-project/cip-testing/linux-stable-rc-ci/-/jobs/1364210937 The other one was not seen today. Uploading binaries 79------------------ 80upload: output/bzImage_siemens_ipc227e_defconfig_5.10.46-rc1_c00b84692/x86/siemens_ipc227e_defconfig/config/.config to s3://download.cip-project.org/ciptesting/ci/bzImage_siemens_ipc227e_defconfig_5.10.46-rc1_c00b84692/x86/siemens_ipc227e_defconfig/config/.config 81upload: output/bzImage_siemens_ipc227e_defconfig_5.10.46-rc1_c00b84692/x86/siemens_ipc227e_defconfig/kernel/bzImage to s3://download.cip-project.org/ciptesting/ci/bzImage_siemens_ipc227e_defconfig_5.10.46-rc1_c00b84692/x86/siemens_ipc227e_defconfig/kernel/bzImage 82upload: output/bzImage_siemens_ipc227e_defconfig_5.10.46-rc1_c00b84692/x86/siemens_ipc227e_defconfig/modules/modules.tar.gz to s3://download.cip-project.org/ciptesting/ci/bzImage_siemens_ipc227e_defconfig_5.10.46-rc1_c00b84692/x86/siemens_ipc227e_defconfig/modules/modules.tar.gz 83fatal error: Could not connect to the endpoint URL: "https://s3.us-west-2.amazonaws.com/download.cip-project.org?list-type=2&prefix=ciptesting%2Fci%2F&continuation-token=1B7XIJq02rzWljriOBePCr8doMhusLUS2jft0k2cLqJDmAxWeWFzs3V30zhXBtgfV87AvBf1P519d7AYS%2Bp7qt3yEDm7KapIDVvcmIAG8WJCA7F3O0u488Gs0%2F7oSTol6DRSt%2Btj3%2FJ4pXB7ZEDL47m4GSSNa0YzUJuMi%2B%2F5MyuaYuejHVTPV5mLw0GBv5oSzxDtIktUYrKcshmrP2CJh5A%3D%3D&encoding-type=url" 85 Uploading artifacts for failed job 01:39 86Uploading artifacts... 87output: found 11 matching files and directories 88ERROR: Uploading artifacts as "archive" to coordinator... error error=couldn't execute POST against https://gitlab.com/api/v4/jobs/1364210937/artifacts?artifact_format=zip&artifact_type=archive&expire_in=1+month: Post https://gitlab.com/api/v4/jobs/1364210937/artifacts?artifact_format=zip&artifact_type=archive&expire_in=1+month: dial tcp: i/o timeout id=1364210937 token=d4_rH_yF 89 Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[PATCH 5.10.y-cip 12/16] spi: spi-mem: Fix passing zero to 'PTR_ERR' warning
Lad Prabhakar
From: YueHaibing <yuehaibing@huawei.com>
commit a9c52d42814a44472fe1205775320ec20f556908 upstream. Fix smatch warning: drivers/spi/spi-mem.c:746 spi_mem_probe() warn: passing zero to 'PTR_ERR' Fixes: 5d27a9c8ea9e ("spi: spi-mem: Extend the SPI mem interface to set a custom memory name") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20201031033042.42892-1-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/spi/spi-mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 4682f49dc733..f3a3f196e628 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -744,7 +744,7 @@ static int spi_mem_probe(struct spi_device *spi) mem->name = dev_name(&spi->dev); if (IS_ERR_OR_NULL(mem->name)) - return PTR_ERR(mem->name); + return PTR_ERR_OR_ZERO(mem->name); spi_set_drvdata(spi, mem); -- 2.17.1
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[PATCH 5.10.y-cip 16/16] dt-bindings: pci: rcar-pci-ep: Document missing interrupts property
Lad Prabhakar
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit f3c6c120614cfb02827ee7bbe6c4240847cc5f12 upstream. The R-Car PCIe controller does not use interrupts when configured for endpoint mode, hence the bindings do not document the interrupts property. However, all DTS files provide interrupts properties, and thus fail to validate. Fix this by documenting the interrupts property. Fixes: 4c0f80920923f103 ("dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20201209101231.2206479-1-geert+renesas@glider.be Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml index 84eeb7fe6e01..295840cf612f 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml @@ -32,6 +32,10 @@ properties: - const: memory2 - const: memory3 + interrupts: + minItems: 3 + maxItems: 3 + power-domains: maxItems: 1 @@ -53,6 +57,7 @@ required: - compatible - reg - reg-names + - interrupts - resets - power-domains - clocks @@ -64,6 +69,7 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a774c0-sysc.h> pcie0_ep: pcie-ep@fe000000 { @@ -75,6 +81,9 @@ examples: <0x30000000 0x8000000>, <0x38000000 0x8000000>; reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; resets = <&cpg 319>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; clocks = <&cpg CPG_MOD 319>; -- 2.17.1
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[PATCH 5.10.y-cip 15/16] dt-bindings: timer: renesas: tmu: Document r8a774e1 bindings
Lad Prabhakar
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
commit db08e6c0e2513d1341369ec6a4f1774ee20b290b upstream. Document RZ/G2H (R8A774E1) SoC in the Renesas TMU bindings. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20201110162014.3290109-2-geert+renesas@glider.be Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- Documentation/devicetree/bindings/timer/renesas,tmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 29159f4e65ab..a36cd61e74fb 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,tmu-r8a774a1" for the r8a774A1 TMU - "renesas,tmu-r8a774b1" for the r8a774B1 TMU - "renesas,tmu-r8a774c0" for the r8a774C0 TMU + - "renesas,tmu-r8a774e1" for the r8a774E1 TMU - "renesas,tmu-r8a7778" for the r8a7778 TMU - "renesas,tmu-r8a7779" for the r8a7779 TMU - "renesas,tmu-r8a77970" for the r8a77970 TMU -- 2.17.1
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[PATCH 5.10.y-cip 14/16] dt-bindings: PCI: rcar-pci-host: Document r8a774e1 bindings
Lad Prabhakar
commit 64fc0a030987eec45c5362618bacdef7227783d5 upstream.
Document the RZ/G2H (a.k.a. R8A774E1) SoC in the R-Car PCIe bingings. [shimoda: minor change the subject and description] Link: https://lore.kernel.org/r/1604455096-13923-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> [PL: Patched text version of binding file] Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 14d307deff06..8e495d6811a0 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -7,6 +7,7 @@ compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC; "renesas,pcie-r8a774a1" for the R8A774A1 SoC; "renesas,pcie-r8a774b1" for the R8A774B1 SoC; "renesas,pcie-r8a774c0" for the R8A774C0 SoC; + "renesas,pcie-r8a774e1" for the R8A774E1 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; -- 2.17.1
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[PATCH 5.10.y-cip 13/16] memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static inline
Lad Prabhakar
commit 7889a7da59e0131ac60b858c73a3604ef88b1d96 upstream.
Define rpcif_enable_rpm() and rpcif_disable_rpm() as static inline in the header instead of exporting them. Suggested-by: Pavel Machek <pavel@denx.de> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Pavel Machek (CIP) <pavel@denx.de> Link: https://lore.kernel.org/r/20201126191146.8753-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/memory/renesas-rpc-if.c | 13 ------------- include/memory/renesas-rpc-if.h | 13 +++++++++++-- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index da0fdb4c7595..8d36e221def1 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -12,7 +12,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> @@ -204,18 +203,6 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev) } EXPORT_SYMBOL(rpcif_sw_init); -void rpcif_enable_rpm(struct rpcif *rpc) -{ - pm_runtime_enable(rpc->dev); -} -EXPORT_SYMBOL(rpcif_enable_rpm); - -void rpcif_disable_rpm(struct rpcif *rpc) -{ - pm_runtime_disable(rpc->dev); -} -EXPORT_SYMBOL(rpcif_disable_rpm); - void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) { u32 dummy; diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 9ad136682c47..14cfd036268a 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -10,6 +10,7 @@ #ifndef __RENESAS_RPC_IF_H #define __RENESAS_RPC_IF_H +#include <linux/pm_runtime.h> #include <linux/types.h> enum rpcif_data_dir { @@ -77,11 +78,19 @@ struct rpcif { int rpcif_sw_init(struct rpcif *rpc, struct device *dev); void rpcif_hw_init(struct rpcif *rpc, bool hyperflash); -void rpcif_enable_rpm(struct rpcif *rpc); -void rpcif_disable_rpm(struct rpcif *rpc); void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, size_t *len); int rpcif_manual_xfer(struct rpcif *rpc); ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf); +static inline void rpcif_enable_rpm(struct rpcif *rpc) +{ + pm_runtime_enable(rpc->dev); +} + +static inline void rpcif_disable_rpm(struct rpcif *rpc) +{ + pm_runtime_disable(rpc->dev); +} + #endif // __RENESAS_RPC_IF_H -- 2.17.1
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[PATCH 5.10.y-cip 10/16] clk: renesas: r8a774b1: Add RPC clocks
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit fb9805c51793339e0affbc8e3ce2b3210b41c9fa upstream. Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20201016121709.8447-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index f436691271ec..6f04c40fe237 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -40,6 +40,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, /* Module Clocks */ @@ -65,6 +66,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A774B1_CLK_RPC), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -196,6 +203,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP), -- 2.17.1
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[PATCH 5.10.y-cip 11/16] clk: renesas: r8a774a1: Add RPC clocks
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 13d2617bf224351e78141183ca51971df83a9dd5 upstream. Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20201016121709.8447-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index fd54b9f625da..4a43ebec7d5e 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -41,6 +41,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, /* Module Clocks */ @@ -67,6 +68,12 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A774A1_CLK_RPC), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP), -- 2.17.1
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[PATCH 5.10.y-cip 06/16] pinctrl: renesas: r8a77951: Add QSPI[01] pins, groups and functions
Lad Prabhakar
commit 590567bf6f6d989ba9d0fc406282d7a18cf5fa96 upstream.
Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201119130926.25692-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/pfc-r8a77951.c | 75 +++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 8d1262c170af..9653324fa15d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -3252,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4160,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[320]; + struct sh_pfc_pin_group common[326]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_pin_group automotive[30]; #endif @@ -4365,6 +4416,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4859,6 +4916,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5047,7 +5116,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[53]; + struct sh_pfc_function common[55]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_function automotive[4]; #endif @@ -5084,6 +5153,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), -- 2.17.1
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[PATCH 5.10.y-cip 07/16] pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0
Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 03522a59a9e7e5f464735e907891cd235aa68b1d upstream. This driver supports both RZ/G2E and R-Car E3 SoCs. Optimize pinctrl image size for RZ/G2E, when support for R-Car E3 (R8A77990) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/pfc-r8a77990.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index aed04a4c6116..6f9f7638703d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1593,6 +1593,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -1785,6 +1786,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -3761,7 +3763,9 @@ static const unsigned int vin5_clk_b_mux[] = { static const struct { struct sh_pfc_pin_group common[247]; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[21]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4012,6 +4016,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk_a), SH_PFC_PIN_GROUP(vin5_clk_b), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4035,6 +4040,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; static const char * const audio_clk_groups[] = { @@ -4088,6 +4094,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4120,6 +4127,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ static const char * const du_groups[] = { "du_rgb666", @@ -4460,7 +4468,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[47]; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4511,12 +4521,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { -- 2.17.1
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