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[PATCH 5.10.y-cip 08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions

Biju Das
 

commit 4decd2e54b61686787f36b727d2772e067a46ea5 upstream.

Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.
1.00, Nov. 2021).

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Acked-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20220126211003.6675-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
include/dt-bindings/clock/r9a07g054-cpg.h | 229 ++++++++++++++++++++++
1 file changed, 229 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h

diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
new file mode 100644
index 000000000000..43f4dbda872c
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G054 CPG Core Clocks */
+#define R9A07G054_CLK_I 0
+#define R9A07G054_CLK_I2 1
+#define R9A07G054_CLK_G 2
+#define R9A07G054_CLK_S0 3
+#define R9A07G054_CLK_S1 4
+#define R9A07G054_CLK_SPI0 5
+#define R9A07G054_CLK_SPI1 6
+#define R9A07G054_CLK_SD0 7
+#define R9A07G054_CLK_SD1 8
+#define R9A07G054_CLK_M0 9
+#define R9A07G054_CLK_M1 10
+#define R9A07G054_CLK_M2 11
+#define R9A07G054_CLK_M3 12
+#define R9A07G054_CLK_M4 13
+#define R9A07G054_CLK_HP 14
+#define R9A07G054_CLK_TSU 15
+#define R9A07G054_CLK_ZT 16
+#define R9A07G054_CLK_P0 17
+#define R9A07G054_CLK_P1 18
+#define R9A07G054_CLK_P2 19
+#define R9A07G054_CLK_AT 20
+#define R9A07G054_OSCCLK 21
+#define R9A07G054_CLK_P0_DIV2 22
+#define R9A07G054_CLK_DRP_M 23
+#define R9A07G054_CLK_DRP_D 24
+#define R9A07G054_CLK_DRP_A 25
+
+/* R9A07G054 Module Clocks */
+#define R9A07G054_CA55_SCLK 0
+#define R9A07G054_CA55_PCLK 1
+#define R9A07G054_CA55_ATCLK 2
+#define R9A07G054_CA55_GICCLK 3
+#define R9A07G054_CA55_PERICLK 4
+#define R9A07G054_CA55_ACLK 5
+#define R9A07G054_CA55_TSCLK 6
+#define R9A07G054_GIC600_GICCLK 7
+#define R9A07G054_IA55_CLK 8
+#define R9A07G054_IA55_PCLK 9
+#define R9A07G054_MHU_PCLK 10
+#define R9A07G054_SYC_CNT_CLK 11
+#define R9A07G054_DMAC_ACLK 12
+#define R9A07G054_DMAC_PCLK 13
+#define R9A07G054_OSTM0_PCLK 14
+#define R9A07G054_OSTM1_PCLK 15
+#define R9A07G054_OSTM2_PCLK 16
+#define R9A07G054_MTU_X_MCK_MTU3 17
+#define R9A07G054_POE3_CLKM_POE 18
+#define R9A07G054_GPT_PCLK 19
+#define R9A07G054_POEG_A_CLKP 20
+#define R9A07G054_POEG_B_CLKP 21
+#define R9A07G054_POEG_C_CLKP 22
+#define R9A07G054_POEG_D_CLKP 23
+#define R9A07G054_WDT0_PCLK 24
+#define R9A07G054_WDT0_CLK 25
+#define R9A07G054_WDT1_PCLK 26
+#define R9A07G054_WDT1_CLK 27
+#define R9A07G054_WDT2_PCLK 28
+#define R9A07G054_WDT2_CLK 29
+#define R9A07G054_SPI_CLK2 30
+#define R9A07G054_SPI_CLK 31
+#define R9A07G054_SDHI0_IMCLK 32
+#define R9A07G054_SDHI0_IMCLK2 33
+#define R9A07G054_SDHI0_CLK_HS 34
+#define R9A07G054_SDHI0_ACLK 35
+#define R9A07G054_SDHI1_IMCLK 36
+#define R9A07G054_SDHI1_IMCLK2 37
+#define R9A07G054_SDHI1_CLK_HS 38
+#define R9A07G054_SDHI1_ACLK 39
+#define R9A07G054_GPU_CLK 40
+#define R9A07G054_GPU_AXI_CLK 41
+#define R9A07G054_GPU_ACE_CLK 42
+#define R9A07G054_ISU_ACLK 43
+#define R9A07G054_ISU_PCLK 44
+#define R9A07G054_H264_CLK_A 45
+#define R9A07G054_H264_CLK_P 46
+#define R9A07G054_CRU_SYSCLK 47
+#define R9A07G054_CRU_VCLK 48
+#define R9A07G054_CRU_PCLK 49
+#define R9A07G054_CRU_ACLK 50
+#define R9A07G054_MIPI_DSI_PLLCLK 51
+#define R9A07G054_MIPI_DSI_SYSCLK 52
+#define R9A07G054_MIPI_DSI_ACLK 53
+#define R9A07G054_MIPI_DSI_PCLK 54
+#define R9A07G054_MIPI_DSI_VCLK 55
+#define R9A07G054_MIPI_DSI_LPCLK 56
+#define R9A07G054_LCDC_CLK_A 57
+#define R9A07G054_LCDC_CLK_P 58
+#define R9A07G054_LCDC_CLK_D 59
+#define R9A07G054_SSI0_PCLK2 60
+#define R9A07G054_SSI0_PCLK_SFR 61
+#define R9A07G054_SSI1_PCLK2 62
+#define R9A07G054_SSI1_PCLK_SFR 63
+#define R9A07G054_SSI2_PCLK2 64
+#define R9A07G054_SSI2_PCLK_SFR 65
+#define R9A07G054_SSI3_PCLK2 66
+#define R9A07G054_SSI3_PCLK_SFR 67
+#define R9A07G054_SRC_CLKP 68
+#define R9A07G054_USB_U2H0_HCLK 69
+#define R9A07G054_USB_U2H1_HCLK 70
+#define R9A07G054_USB_U2P_EXR_CPUCLK 71
+#define R9A07G054_USB_PCLK 72
+#define R9A07G054_ETH0_CLK_AXI 73
+#define R9A07G054_ETH0_CLK_CHI 74
+#define R9A07G054_ETH1_CLK_AXI 75
+#define R9A07G054_ETH1_CLK_CHI 76
+#define R9A07G054_I2C0_PCLK 77
+#define R9A07G054_I2C1_PCLK 78
+#define R9A07G054_I2C2_PCLK 79
+#define R9A07G054_I2C3_PCLK 80
+#define R9A07G054_SCIF0_CLK_PCK 81
+#define R9A07G054_SCIF1_CLK_PCK 82
+#define R9A07G054_SCIF2_CLK_PCK 83
+#define R9A07G054_SCIF3_CLK_PCK 84
+#define R9A07G054_SCIF4_CLK_PCK 85
+#define R9A07G054_SCI0_CLKP 86
+#define R9A07G054_SCI1_CLKP 87
+#define R9A07G054_IRDA_CLKP 88
+#define R9A07G054_RSPI0_CLKB 89
+#define R9A07G054_RSPI1_CLKB 90
+#define R9A07G054_RSPI2_CLKB 91
+#define R9A07G054_CANFD_PCLK 92
+#define R9A07G054_GPIO_HCLK 93
+#define R9A07G054_ADC_ADCLK 94
+#define R9A07G054_ADC_PCLK 95
+#define R9A07G054_TSU_PCLK 96
+#define R9A07G054_STPAI_INITCLK 97
+#define R9A07G054_STPAI_ACLK 98
+#define R9A07G054_STPAI_MCLK 99
+#define R9A07G054_STPAI_DCLKIN 100
+#define R9A07G054_STPAI_ACLK_DRP 101
+
+/* R9A07G054 Resets */
+#define R9A07G054_CA55_RST_1_0 0
+#define R9A07G054_CA55_RST_1_1 1
+#define R9A07G054_CA55_RST_3_0 2
+#define R9A07G054_CA55_RST_3_1 3
+#define R9A07G054_CA55_RST_4 4
+#define R9A07G054_CA55_RST_5 5
+#define R9A07G054_CA55_RST_6 6
+#define R9A07G054_CA55_RST_7 7
+#define R9A07G054_CA55_RST_8 8
+#define R9A07G054_CA55_RST_9 9
+#define R9A07G054_CA55_RST_10 10
+#define R9A07G054_CA55_RST_11 11
+#define R9A07G054_CA55_RST_12 12
+#define R9A07G054_GIC600_GICRESET_N 13
+#define R9A07G054_GIC600_DBG_GICRESET_N 14
+#define R9A07G054_IA55_RESETN 15
+#define R9A07G054_MHU_RESETN 16
+#define R9A07G054_DMAC_ARESETN 17
+#define R9A07G054_DMAC_RST_ASYNC 18
+#define R9A07G054_SYC_RESETN 19
+#define R9A07G054_OSTM0_PRESETZ 20
+#define R9A07G054_OSTM1_PRESETZ 21
+#define R9A07G054_OSTM2_PRESETZ 22
+#define R9A07G054_MTU_X_PRESET_MTU3 23
+#define R9A07G054_POE3_RST_M_REG 24
+#define R9A07G054_GPT_RST_C 25
+#define R9A07G054_POEG_A_RST 26
+#define R9A07G054_POEG_B_RST 27
+#define R9A07G054_POEG_C_RST 28
+#define R9A07G054_POEG_D_RST 29
+#define R9A07G054_WDT0_PRESETN 30
+#define R9A07G054_WDT1_PRESETN 31
+#define R9A07G054_WDT2_PRESETN 32
+#define R9A07G054_SPI_RST 33
+#define R9A07G054_SDHI0_IXRST 34
+#define R9A07G054_SDHI1_IXRST 35
+#define R9A07G054_GPU_RESETN 36
+#define R9A07G054_GPU_AXI_RESETN 37
+#define R9A07G054_GPU_ACE_RESETN 38
+#define R9A07G054_ISU_ARESETN 39
+#define R9A07G054_ISU_PRESETN 40
+#define R9A07G054_H264_X_RESET_VCP 41
+#define R9A07G054_H264_CP_PRESET_P 42
+#define R9A07G054_CRU_CMN_RSTB 43
+#define R9A07G054_CRU_PRESETN 44
+#define R9A07G054_CRU_ARESETN 45
+#define R9A07G054_MIPI_DSI_CMN_RSTB 46
+#define R9A07G054_MIPI_DSI_ARESET_N 47
+#define R9A07G054_MIPI_DSI_PRESET_N 48
+#define R9A07G054_LCDC_RESET_N 49
+#define R9A07G054_SSI0_RST_M2_REG 50
+#define R9A07G054_SSI1_RST_M2_REG 51
+#define R9A07G054_SSI2_RST_M2_REG 52
+#define R9A07G054_SSI3_RST_M2_REG 53
+#define R9A07G054_SRC_RST 54
+#define R9A07G054_USB_U2H0_HRESETN 55
+#define R9A07G054_USB_U2H1_HRESETN 56
+#define R9A07G054_USB_U2P_EXL_SYSRST 57
+#define R9A07G054_USB_PRESETN 58
+#define R9A07G054_ETH0_RST_HW_N 59
+#define R9A07G054_ETH1_RST_HW_N 60
+#define R9A07G054_I2C0_MRST 61
+#define R9A07G054_I2C1_MRST 62
+#define R9A07G054_I2C2_MRST 63
+#define R9A07G054_I2C3_MRST 64
+#define R9A07G054_SCIF0_RST_SYSTEM_N 65
+#define R9A07G054_SCIF1_RST_SYSTEM_N 66
+#define R9A07G054_SCIF2_RST_SYSTEM_N 67
+#define R9A07G054_SCIF3_RST_SYSTEM_N 68
+#define R9A07G054_SCIF4_RST_SYSTEM_N 69
+#define R9A07G054_SCI0_RST 70
+#define R9A07G054_SCI1_RST 71
+#define R9A07G054_IRDA_RST 72
+#define R9A07G054_RSPI0_RST 73
+#define R9A07G054_RSPI1_RST 74
+#define R9A07G054_RSPI2_RST 75
+#define R9A07G054_CANFD_RSTP_N 76
+#define R9A07G054_CANFD_RSTC_N 77
+#define R9A07G054_GPIO_RSTN 78
+#define R9A07G054_GPIO_PORT_RESETN 79
+#define R9A07G054_GPIO_SPARE_RESETN 80
+#define R9A07G054_ADC_PRESETN 81
+#define R9A07G054_ADC_ADRST_N 82
+#define R9A07G054_TSU_PRESETN 83
+#define R9A07G054_STPAI_ARESETN 84
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
--
2.25.1


[PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3

Biju Das
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>

commit b289cdecc7c3e25e001cde260c882e4d9a8b0772 upstream.

As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be
1600 MHz, but with current multiplier and divider values this resulted
to 1596 MHz.

This patch updates the multiplier and divider values for PLL2 and PLL3
so that we get the exact (1600 MHz) values.

Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC")
Suggested-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 79042bf46fe8..46359afef0d4 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -88,8 +88,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
- DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
- DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),

--
2.25.1


[PATCH 5.10.y-cip 06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries

Biju Das
 

commit f0b62b0bbedcdfde18116080605cebd9beec4ee9 upstream.

Add GPU clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/clk/renesas/r9a07g044-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 85132b6c97b7..79042bf46fe8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -198,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x554, 6),
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
0x554, 7),
+ DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
+ 0x558, 0),
+ DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
+ 0x558, 1),
+ DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
+ 0x558, 2),
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
0x570, 0),
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -285,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
+ DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
+ DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
+ DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
--
2.25.1


[PATCH 5.10.y-cip 05/24] clk: renesas: r9a07g044: Add mux and divider for G clock

Biju Das
 

commit 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 upstream.

G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.

This patch adds a mux and divider for getting different rates from
this clock sources.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/clk/renesas/r9a07g044-cpg.c | 6 ++++++
drivers/clk/renesas/rzg2l-cpg.h | 4 ++++
2 files changed, 10 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0962f25cd3f0..85132b6c97b7 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -50,6 +50,7 @@ enum clk_ids {
CLK_PLL2_SDHI_266,
CLK_SD0_DIV4,
CLK_SD1_DIV4,
+ CLK_SEL_GPU2,

/* Module Clocks */
MOD_CLK_BASE,
@@ -77,6 +78,7 @@ static const struct clk_div_table dtable_1_32[] = {
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
+static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };

static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* External Clock Inputs */
@@ -116,6 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {

DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
+ DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
+ sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),

/* Core output clk */
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -141,6 +145,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
sel_shdi, ARRAY_SIZE(sel_shdi)),
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
+ DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
+ CLK_DIVIDER_HIWORD_MASK),
};

static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index fce4a8f35410..5729d102034b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -12,9 +12,11 @@
#define CPG_PL1_DDIV (0x200)
#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
+#define CPG_PL6_DDIV (0x210)
#define CPG_PL2SDHI_DSEL (0x218)
#define CPG_CLKSTATUS (0x280)
#define CPG_PL3_SSEL (0x408)
+#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)

#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
@@ -35,12 +37,14 @@
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
+#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)

#define SEL_PLL_PACK(offset, bitpos, size) \
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))

#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
+#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)

#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
--
2.25.1


[PATCH 5.10.y-cip 04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform

Biju Das
 

commit 81a27b1f69022174567e8237d3de2534821671ba upstream.

Enable the microSD card slot connected to SDHI1 on the RZ/G2LC SMARC
platform by removing the sdhi1 override which disabled it, and by adding
the necessary pinmux required for SDHI1.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220117075130.6198-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 8 ----
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 39 +++++++++++++++++++
2 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 728a2275ea8d..8d671111d973 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -81,14 +81,6 @@ &scif2 {
status = "disabled";
};

-&sdhi1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-1;
- /delete-property/ pinctrl-names;
- /delete-property/ vmmc-supply;
- status = "disabled";
-};
-
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 5333a1f9a0e7..1032f6563515 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -17,6 +17,45 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};

+ sd1-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sd1_pwr_en";
+ };
+
+ sdhi1_pins: sd1 {
+ sd1_data {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <3300>;
+ };
+
+ sd1_ctrl {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ sd1_mux {
+ pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+ };
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ sd1_data_uhs {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <1800>;
+ };
+
+ sd1_ctrl_uhs {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <1800>;
+ };
+
+ sd1_mux_uhs {
+ pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+ };
+ };
+
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
--
2.25.1


[PATCH 5.10.y-cip 03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform

Biju Das
 

commit 7ca0ce6478c6803c9f86e7366f5634de9c096207 upstream.

RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0.

Both these interfaces are mutually exclusive and the SD0 device
selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2]
switch position.

This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch
setting logic for device selection between eMMC and microSD slot
connected to SDHI0.

Set SW1[2] to position OFF for selecting eMMC
Set SW1[2] to position ON for selecting microSD

This patch enables eMMC on RZ/G2LC SMARC platform by default.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220117075130.6198-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 142 ++++++++++++++++++
1 file changed, 142 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index e1d7a3a689c6..6ebda3724f2c 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -8,6 +8,16 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

+/* SW1[2] should be at OFF position to enable 64 GB eMMC */
+#define EMMC 1
+
+/*
+ * To enable uSD card on CN3,
+ * SW1[2] should be at ON position.
+ * Disable eMMC by setting "#define EMMC 0" above.
+ */
+#define SDHI (!EMMC)
+
/ {
aliases {
ethernet0 = &eth0;
@@ -22,6 +32,36 @@ memory@48000000 {
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 1>, <1800000 0>;
+ regulator-boot-on;
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ };
};

&eth0 {
@@ -72,5 +112,107 @@ eth0_pins: eth0 {
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
+
+ gpio-sd0-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "gpio_sd0_pwr_en";
+ };
+
+ /*
+ * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
+ * The below switch logic can be used to select the device between
+ * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
+ * SW1[2] should be at OFF position to enable 64 GB eMMC
+ * SW1[2] should be at position ON to enable uSD card CN3
+ */
+ gpio-sd0-dev-sel-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "gpio_sd0_dev_sel";
+ };
+
+ sdhi0_emmc_pins: sd0emmc {
+ sd0_emmc_data {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <1800>;
+ };
+
+ sd0_emmc_ctrl {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sd0_emmc_rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+ };
+
+ sdhi0_pins: sd0 {
+ sd0_data {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
+ power-source = <3300>;
+ };
+
+ sd0_ctrl {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ sd0_mux {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
+ };
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ sd0_data_uhs {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
+ power-source = <1800>;
+ };
+
+ sd0_ctrl_uhs {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sd0_mux_uhs {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
+ };
+ };
+};
+
+#if SDHI
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+#endif
+
+#if EMMC
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_emmc_pins>;
+ pinctrl-1 = <&sdhi0_emmc_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
};
+#endif

--
2.25.1


[PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK

Biju Das
 

commit ce0c63b6a5ef86208d1008ce6c42a7a7180aaf75 upstream.

Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211216114305.5842-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 114 ++++++++++++++++++
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 25 ++++
.../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 76 ++++++++++++
4 files changed, 216 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8a5bc12a6d8d..962a66332236 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -57,4 +57,5 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb

dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb

+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
new file mode 100644
index 000000000000..728a2275ea8d
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044c2.dtsi"
+#include "rzg2lc-smarc-som.dtsi"
+#include "rzg2lc-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g044c2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
+
+};
+
+&canfd {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ehci0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ehci1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&hsusb {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c3 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ohci0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ohci1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&scif2 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&sdhi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-1;
+ /delete-property/ pinctrl-names;
+ /delete-property/ vmmc-supply;
+ status = "disabled";
+};
+
+&spi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ssi0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
new file mode 100644
index 000000000000..5333a1f9a0e7
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&pinctrl {
+ pinctrl-0 = <&sound_clk_pins>;
+ pinctrl-names = "default";
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
+ };
+
+ sound_clk_pins: sound_clk {
+ pins = "AUDIO_CLK1", "AUDIO_CLK2";
+ input-enable;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
new file mode 100644
index 000000000000..e1d7a3a689c6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+ aliases {
+ ethernet0 = &eth0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+};
+
+&eth0 {
+ pinctrl-0 = <&eth0_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ rxc-skew-psec = <2400>;
+ txc-skew-psec = <2400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+};
+
--
2.25.1


[PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC

Biju Das
 

commit 3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd upstream.

The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID.
RZ/G2LC has fewer peripherals compared to RZ/G2L.

SSI (3 channels vs 4 channels)
GbEthernet (1 channel vs 2 channels)
SCIFA (4 channels vs 5 channels)
ADC is only supported in RZ/G2L.

Add the initial DTSI for the RZ/G2LC SoC by reusing the common
r9a07g044.dtsi file with unsupported device nodes deleted in the below
SoC specific dtsi files.

r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts
r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20211216114305.5842-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 32 ++++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi | 20 ++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
new file mode 100644
index 000000000000..1d57df706939
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044c1", "renesas,r9a07g044";
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ };
+
+ timer {
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+&soc {
+ /delete-node/ ssi@1004a800;
+ /delete-node/ serial@1004c800;
+ /delete-node/ adc@10059000;
+ /delete-node/ ethernet@11c30000;
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
new file mode 100644
index 000000000000..7bb8917fe421
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044c2", "renesas,r9a07g044";
+};
+
+&soc {
+ /delete-node/ ssi@1004a800;
+ /delete-node/ serial@1004c800;
+ /delete-node/ adc@10059000;
+ /delete-node/ ethernet@11c30000;
+};
--
2.25.1


[PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support

Biju Das
 

This patch series aims to add Basic board support for SMARC EVK
based on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same
SMARC EVK board, but SoM is different and pin mapping of SoM
module is different.

All these patches are cherry-picked from the mainline.

Subsequent patch series will add more functionality to these platforms.

RZ/G2LC SMARC EVK logs:
root@smarc-rzg2lc:~# cat /sys/devices/soc0/family
RZ/G2L
root@smarc-rzg2lc:~# cat /sys/devices/soc0/machine
Renesas SMARC EVK based on r9a07g044c2
root@smarc-rzg2lc:~# cat /sys/devices/soc0/revision
1
root@smarc-rzg2lc:~# cat /sys/devices/soc0/soc_id
r9a07g044
root@smarc-rzg2lc:~# dmesg | grep Detect
[ 0.003208] Detected Renesas RZ/G2L r9a07g044 Rev 1

RZ/V2L SMARC EVK logs:
root@smarc-rzv2l:~# cat /sys/devices/soc0/family
RZ/V2L
root@smarc-rzv2l:~# cat /sys/devices/soc0/machine
Renesas SMARC EVK based on r9a07g054l2
root@smarc-rzv2l:~# cat /sys/devices/soc0/revision
0
root@smarc-rzv2l:~# cat /sys/devices/soc0/soc_id
r9a07g054
root@smarc-rzv2l:~# dmesg | grep Detect
[ 0.003260] Detected Renesas RZ/V2L r9a07g054 Rev 0

Biju Das (20):
arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
clk: renesas: r9a07g044: Add mux and divider for G clock
clk: renesas: r9a07g044: Add GPU clock and reset entries
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
dt-bindings: clock: renesas: Document RZ/V2L SoC
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
dt-bindings: serial: renesas,scif: Document RZ/V2L SoC
dt-bindings: serial: renesas,sci: Document RZ/V2L SoC
dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl
pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is
enabled
pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register()
dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board

Geert Uytterhoeven (1):
clk: renesas: rzg2l: Simplify multiplication/shift logic

Lad Prabhakar (2):
clk: renesas: r9a07g044: Update multiplier and divider values for
PLL2/3
arm64: defconfig: Enable ARCH_R9A07G054

Phil Edworthy (1):
clk: renesas: rzg2l: Remove unused notifiers

.../bindings/clock/renesas,rzg2l-cpg.yaml | 14 +-
.../bindings/net/renesas,etheravb.yaml | 3 +-
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +-
.../bindings/serial/renesas,sci.yaml | 2 +
.../bindings/serial/renesas,scif.yaml | 7 +
arch/arm64/boot/dts/renesas/Makefile | 3 +
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 32 ++
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 97 ++++
arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi | 20 +
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 ++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 +
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 26 +
arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 +
.../boot/dts/renesas/rz-smarc-common.dtsi | 207 ++++++++
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +-
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +-
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 195 +------
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 71 +++
.../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 218 ++++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 62 +++
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 421 ++++++++-------
drivers/clk/renesas/rzg2l-cpg.c | 10 +-
drivers/clk/renesas/rzg2l-cpg.h | 5 +
drivers/pinctrl/renesas/Kconfig | 6 +-
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 +-
include/dt-bindings/clock/r9a07g054-cpg.h | 229 ++++++++
30 files changed, 1795 insertions(+), 395 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h

--
2.25.1


Re: [isar-cip-core][RFC 0/2] clean up kas/opt

Jan Kiszka
 

On 01.08.22 16:57, Quirin Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@...>

Remove the kas option for efibootguard as it cannot build a image.
Move the package installation for swupdate to the include.

Quirin Gylstorff (2):
kas: Remove efibootguard.yml
kas/opt/swupdate: Move the package installation to swupdate.inc

kas/opt/ebg-secure-boot-snakeoil.yml | 10 +++----
kas/opt/ebg-swu.yml | 9 +++----
kas/opt/efibootguard.yml | 39 ----------------------------
kas/opt/swupdate.yml | 4 ---
recipes-core/images/efibootguard.inc | 26 +++++++++++++++++++
recipes-core/images/swupdate.inc | 3 +++
6 files changed, 36 insertions(+), 55 deletions(-)
delete mode 100644 kas/opt/efibootguard.yml
create mode 100644 recipes-core/images/efibootguard.inc
Thanks, applied.

Jan

--
Siemens AG, Technology
Competence Center Embedded Linux


Re: [isar-cip-core][PATCH v2 0/4] Add support for ISAR with sbuild

Jan Kiszka
 

On 29.07.22 12:04, Quirin Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@...>

This patch series integrates ISAR with the Sbuild feature.

Changes in V2:
- reoder patches

Quirin Gylstorff (4):
scripts/deploy-cip-core.sh: Use dtb from deploy dir
recipes-devtools/ovmf-binaries: Adapt to sbuild environment
kas-cip: Add patch for linux-cip with CONFIG_MODULES=n
Update ISAR for sbuild integration

.gitlab-ci.yml | 6 ++--
conf/machine/bbb.conf | 1 +
...ernel-Check-if-CONFIG_MODULES-is-set.patch | 33 +++++++++++++++++++
kas-cip.yml | 6 +++-
.../ovmf-binaries/files/control.tmpl | 11 -------
recipes-devtools/ovmf-binaries/files/rules | 17 ++++++++++
.../ovmf-binaries/ovmf-binaries_0.1.bb | 18 ++++++----
scripts/deploy-cip-core.sh | 2 +-
8 files changed, 71 insertions(+), 23 deletions(-)
create mode 100644 isar-patches/0001-recipes-kernel-Check-if-CONFIG_MODULES-is-set.patch
delete mode 100644 recipes-devtools/ovmf-binaries/files/control.tmpl
create mode 100644 recipes-devtools/ovmf-binaries/files/rules
Thanks, applied.

Jan

--
Siemens AG, Technology
Competence Center Embedded Linux


[ANNOUNCE] Release v4.4.302-cip70

Nobuhiro Iwamatsu
 

[ANNOUNCE] Release v4.4.302-cip70

Hi all,

CIP kernel team has released Linux kernel v4.4.302-cip70.
This applies the required fixes for 4.4.y up to 4.9.320 of the 4.9.y tree.
You can get this release via the git tree at:

v4.4.302-cip70:
repository:
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git
branch:
linux-4.4.y-cip
commit hash:
42722e64d359f47f84e170ac99e4b2dd2d04865b
Fixed CVEs:
CVE-2022-23038: xen/grant-table: add gnttab_try_end_foreign_access()
CVE-2022-23039: xen/gntalloc: don't use gnttab_query_foreign_access()
CVE-2022-23036: xen/grant-table: add gnttab_try_end_foreign_access()
CVE-2022-23037: xen/netfront: don't use gnttab_query_foreign_access() for mapped status
CVE-2022-0001: x86/speculation: Rename RETPOLINE_AMD to RETPOLINE_LFENCE
CVE-2022-0002: x86/speculation: Rename RETPOLINE_AMD to RETPOLINE_LFENCE
CVE-2021-26401: x86/speculation: Use generic retpoline by default on AMD
CVE-2022-23040: xen/xenbus: don't let xenbus_grant_ring() remove grants in error case
CVE-2022-23042: xen/netfront: react properly to failing gnttab_end_foreign_access_ref()
CVE-2022-1199: ax25: Fix NULL pointer dereference in ax25_kill_by_device
CVE-2021-4149: btrfs: unlock newly allocated extent buffer after error
CVE-2022-26490: nfc: st21nfca: Fix potential buffer overflows in EVT_TRANSACTION
CVE-2022-28356: llc: fix netdevice reference leaks in llc_ui_bind()
CVE-2022-1016: netfilter: nf_tables: initialize registers in nft_do_chain()
CVE-2022-1198: drivers: hamradio: 6pack: fix UAF bug caused by mod_timer()
CVE-2022-1353: af_key: add __GFP_ZERO flag for compose_sadb_supported in function pfkey_register
CVE-2022-28390: can: ems_usb: ems_usb_start_xmit(): fix double dev_kfree_skb() in error path
CVE-2022-30594: ptrace: Check PTRACE_O_SUSPEND_SECCOMP permission on PTRACE_SEIZE
CVE-2022-2380: video: fbdev: sm712fb: Fix crash in smtcfb_read()
CVE-2022-33981: floppy: disable FDRAWCMD by default
CVE-2022-1974: nfc: replace improper check device_is_registered() in netlink related functions
CVE-2022-1975: NFC: netlink: fix sleep in atomic bug when firmware download timeout
CVE-2022-1734: nfc: nfcmrvl: main: reorder destructive operations in nfcmrvl_nci_unregister_dev to avoid bugs
CVE-2022-1836: floppy: disable FDRAWCMD by default
CVE-2022-1652: floppy: use a statically allocated error counter
CVE-2022-1729: perf: Fix sys_perf_event_open() race against self
CVE-2022-0494: block-map: add __GFP_ZERO flag for alloc_page in function bio_copy_kern
CVE-2022-1184: ext4: verify dir block before splitting it
CVE-2022-32981: powerpc/32: Fix overread/overwrite of thread_struct via ptrace
CVE-2022-32296: tcp: increase source port perturb table to 2^16
CVE-2022-1011: fuse: fix pipe buffer lifetime for direct_io
CVE-2022-1012: secure_seq: use the 64 bits of the siphash for port offset calculation
added commits:
CIP: Bump version suffix to -cip70 after merge from stable

Best regards,
Nobuhiro


[isar-cip-core][RFC 0/2] clean up kas/opt

Quirin Gylstorff
 

From: Quirin Gylstorff <quirin.gylstorff@...>

Remove the kas option for efibootguard as it cannot build a image.
Move the package installation for swupdate to the include.

Quirin Gylstorff (2):
kas: Remove efibootguard.yml
kas/opt/swupdate: Move the package installation to swupdate.inc

kas/opt/ebg-secure-boot-snakeoil.yml | 10 +++----
kas/opt/ebg-swu.yml | 9 +++----
kas/opt/efibootguard.yml | 39 ----------------------------
kas/opt/swupdate.yml | 4 ---
recipes-core/images/efibootguard.inc | 26 +++++++++++++++++++
recipes-core/images/swupdate.inc | 3 +++
6 files changed, 36 insertions(+), 55 deletions(-)
delete mode 100644 kas/opt/efibootguard.yml
create mode 100644 recipes-core/images/efibootguard.inc

--
2.35.1


[isar-cip-core][RFC 1/2] kas: Remove efibootguard.yml

Quirin Gylstorff
 

From: Quirin Gylstorff <quirin.gylstorff@...>

A build with only the option `kas/efibootguard.yml` will not succeed.
Move the content to a include in the image directory and the adapt the kas
files.

Signed-off-by: Quirin Gylstorff <quirin.gylstorff@...>
---
kas/opt/ebg-secure-boot-snakeoil.yml | 10 +++----
kas/opt/ebg-swu.yml | 9 +++----
kas/opt/efibootguard.yml | 39 ----------------------------
recipes-core/images/efibootguard.inc | 26 +++++++++++++++++++
4 files changed, 33 insertions(+), 51 deletions(-)
delete mode 100644 kas/opt/efibootguard.yml
create mode 100644 recipes-core/images/efibootguard.inc

diff --git a/kas/opt/ebg-secure-boot-snakeoil.yml b/kas/opt/ebg-secure-boot-snakeoil.yml
index 2822cef..4730ef4 100644
--- a/kas/opt/ebg-secure-boot-snakeoil.yml
+++ b/kas/opt/ebg-secure-boot-snakeoil.yml
@@ -11,16 +11,12 @@

header:
version: 10
- includes:
- - kas/opt/efibootguard.yml

local_conf_header:
+ ebg_swu_bootloader: |
+ SWUPDATE_BOOTLOADER = "efibootguard"
image-options-swupdate: |
- CIP_IMAGE_OPTIONS_append = " swupdate.inc"
-
- swupdate: |
- IMAGE_INSTALL_append = " swupdate"
- IMAGE_INSTALL_append = " swupdate-handler-roundrobin"
+ CIP_IMAGE_OPTIONS_append = " swupdate.inc efibootguard.inc"

secure-boot-image: |
IMAGE_CLASSES += "verity"
diff --git a/kas/opt/ebg-swu.yml b/kas/opt/ebg-swu.yml
index 5e4e771..43d6080 100644
--- a/kas/opt/ebg-swu.yml
+++ b/kas/opt/ebg-swu.yml
@@ -11,13 +11,12 @@

header:
version: 10
- includes:
- - kas/opt/efibootguard.yml
- - kas/opt/swupdate.yml

local_conf_header:
+ ebg_swu_bootloader: |
+ SWUPDATE_BOOTLOADER = "efibootguard"
+ ebg_swu_image_options: |
+ CIP_IMAGE_OPTIONS_append = " swupdate.inc efibootguard.inc image-uuid.inc"
initramfs: |
INITRAMFS_INSTALL_append = " initramfs-abrootfs-hook"

- image-option-uuid: |
- CIP_IMAGE_OPTIONS_append = " image-uuid.inc"
diff --git a/kas/opt/efibootguard.yml b/kas/opt/efibootguard.yml
deleted file mode 100644
index cee9c78..0000000
--- a/kas/opt/efibootguard.yml
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# CIP Core, generic profile
-#
-# Copyright (c) Siemens AG, 2020
-#
-# Authors:
-# Quirin Gylstorff <quirin.gylstorff@...>
-#
-# SPDX-License-Identifier: MIT
-#
-# This kas file adds efibootguard as the bootloader to the image
-
-header:
- version: 10
-
-local_conf_header:
- efibootguard: |
- IMAGE_INSTALL_append = " efibootguard"
-
- efibootguard-swupdate: |
- SWUPDATE_BOOTLOADER = "efibootguard"
-
- efibootguard-wic: |
- WIC_IMAGER_INSTALL_append = " efibootguard"
- WDOG_TIMEOUT ?= "60"
- WICVARS += "WDOG_TIMEOUT KERNEL_IMAGE INITRD_IMAGE DTB_FILES"
- IMAGE_FSTYPES ?= "wic"
- WKS_FILE ?= "${MACHINE}-efibootguard.wks.in"
-
- firmware-binaries: |
- # Add ovmf binaries for qemu
- IMAGER_BUILD_DEPS_append_qemu-amd64 += "ovmf-binaries"
- # not needed for Debian 11 and later
- OVERRIDES_append_qemu-amd64 = ":${BASE_DISTRO_CODENAME}"
- DISTRO_APT_SOURCES_append_qemu-amd64_buster = " conf/distro/debian-buster-backports.list"
- DISTRO_APT_PREFERENCES_append_qemu-amd64_buster = " conf/distro/preferences.ovmf-snakeoil.conf"
- # Add U-Boot for qemu
- IMAGER_BUILD_DEPS_append_qemu-arm64 += "u-boot-qemu-arm64"
- IMAGER_BUILD_DEPS_append_qemu-arm += "u-boot-qemu-arm"
diff --git a/recipes-core/images/efibootguard.inc b/recipes-core/images/efibootguard.inc
new file mode 100644
index 0000000..63bbf91
--- /dev/null
+++ b/recipes-core/images/efibootguard.inc
@@ -0,0 +1,26 @@
+#
+# CIP Core, generic profile
+#
+# Copyright (c) Siemens AG, 2020
+#
+# Authors:
+# Quirin Gylstorff <quirin.gylstorff@...>
+#
+# SPDX-License-Identifier: MIT
+#
+
+IMAGE_INSTALL_append = " efibootguard"
+
+WIC_IMAGER_INSTALL_append = " efibootguard"
+WDOG_TIMEOUT ?= "60"
+WICVARS += "WDOG_TIMEOUT"
+
+# Add ovmf binaries for qemu
+IMAGER_BUILD_DEPS_append_qemu-amd64 += "ovmf-binaries"
+# not needed for Debian 11 and later
+OVERRIDES_append_qemu-amd64 = ":${BASE_DISTRO_CODENAME}"
+DISTRO_APT_SOURCES_append_qemu-amd64_buster = " conf/distro/debian-buster-backports.list"
+DISTRO_APT_PREFERENCES_append_qemu-amd64_buster = " conf/distro/preferences.ovmf-snakeoil.conf"
+# Add U-Boot for qemu
+IMAGER_BUILD_DEPS_append_qemu-arm64 += "u-boot-qemu-arm64"
+IMAGER_BUILD_DEPS_append_qemu-arm += "u-boot-qemu-arm"
--
2.35.1


[isar-cip-core][RFC 2/2] kas/opt/swupdate: Move the package installation to swupdate.inc

Quirin Gylstorff
 

From: Quirin Gylstorff <quirin.gylstorff@...>

Signed-off-by: Quirin Gylstorff <quirin.gylstorff@...>
---
kas/opt/swupdate.yml | 4 ----
recipes-core/images/swupdate.inc | 3 +++
2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/kas/opt/swupdate.yml b/kas/opt/swupdate.yml
index c2bd15c..8ba03c9 100644
--- a/kas/opt/swupdate.yml
+++ b/kas/opt/swupdate.yml
@@ -15,10 +15,6 @@ header:
version: 10

local_conf_header:
- swupdate: |
- IMAGE_INSTALL_append = " swupdate"
- IMAGE_INSTALL_append = " swupdate-handler-roundrobin"
-
image-option-swupdate: |
CIP_IMAGE_OPTIONS_append = " swupdate.inc"

diff --git a/recipes-core/images/swupdate.inc b/recipes-core/images/swupdate.inc
index e0252df..edc41a0 100644
--- a/recipes-core/images/swupdate.inc
+++ b/recipes-core/images/swupdate.inc
@@ -12,6 +12,9 @@
inherit swupdate
inherit read-only-rootfs

+IMAGE_INSTALL += " swupdate"
+IMAGE_INSTALL += " swupdate-handler-roundrobin"
+
ROOTFS_PARTITION_NAME = "${IMAGE_FULLNAME}.wic.p4.gz"

FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
--
2.35.1


lab-cip-renesas offline

Chris Paterson
 

Hi all,

Just a heads-up that lab-cip-renesas is currently offline due to some networking issues.
Hopefully it'll be back up again today, IT gods willing.

Apologies for the inconvenience.

Kind regards, Chris


cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc smc: 5 runs, 2 regressions (v4.19.252-cip78-113-gb7034e0f773f8) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc smc: 5 runs, 2 regressions (v4.19.252-cip78-113-gb7034e0f773f8)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
----------------------+-------+-------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig | 1
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fiwamatsu%2Flinux-4.19.y-cip-rc/kernel/v4.19.252-cip78-113-gb7034e0f773f8/plan/smc/

Test: smc
Tree: cip-gitlab
Branch: ci/iwamatsu/linux-4.19.y-cip-rc
Describe: v4.19.252-cip78-113-gb7034e0f773f8
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: b7034e0f773f811f76bd4c5795f4eafe7e1dede9


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
----------------------+-------+-------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e453504e51464ebadaf08b

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/smc-qemu_arm64-virt-gicv3.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/smc-qemu_arm64-virt-gicv3.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* smc.login: https://kernelci.org/test/case/id/62e453504e51464ebadaf08c
failing since 53 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.245-cip74-32-g2d021d7a9e637)



platform | arch | lab | compiler | defconfig | regressions
----------------------+-------+-------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e454b8ed5011c8efdaf073

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/smc-qemu_arm64-virt-gicv3.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/smc-qemu_arm64-virt-gicv3.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* smc.login: https://kernelci.org/test/case/id/62e454b8ed5011c8efdaf074
failing since 53 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.245-cip74-32-g2d021d7a9e637)


cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc kselftest-futex: 6 runs, 1 regressions (v4.19.252-cip78-113-gb7034e0f773f8) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc kselftest-futex: 6 runs, 1 regressions (v4.19.252-cip78-113-gb7034e0f773f8)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
-------------------------+-------+---------+----------+-----------+------------
r8a774a1-hihope-rzg2m-ex | arm64 | lab-cip | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fiwamatsu%2Flinux-4.19.y-cip-rc/kernel/v4.19.252-cip78-113-gb7034e0f773f8/plan/kselftest-futex/

Test: kselftest-futex
Tree: cip-gitlab
Branch: ci/iwamatsu/linux-4.19.y-cip-rc
Describe: v4.19.252-cip78-113-gb7034e0f773f8
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: b7034e0f773f811f76bd4c5795f4eafe7e1dede9


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
-------------------------+-------+---------+----------+-----------+------------
r8a774a1-hihope-rzg2m-ex | arm64 | lab-cip | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e454500fd6d6456cdaf056

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-cip/kselftest-futex-r8a774a1-hihope-rzg2m-ex.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-cip/kselftest-futex-r8a774a1-hihope-rzg2m-ex.html
Rootfs: http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20220718.0/arm64/initrd.cpio.gz


* kselftest-futex.login: https://kernelci.org/test/case/id/62e454500fd6d6456cdaf057
failing since 7 days (last pass: v4.19.249-cip76-57-gef3cc1b9e556, first fail: v4.19.251-cip77-82-g10c370b53152)


cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc kselftest-filesystems: 4 runs, 1 regressions (v4.19.252-cip78-113-gb7034e0f773f8) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc kselftest-filesystems: 4 runs, 1 regressions (v4.19.252-cip78-113-gb7034e0f773f8)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
-------------------------+-------+---------+----------+-----------+------------
r8a774a1-hihope-rzg2m-ex | arm64 | lab-cip | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fiwamatsu%2Flinux-4.19.y-cip-rc/kernel/v4.19.252-cip78-113-gb7034e0f773f8/plan/kselftest-filesystems/

Test: kselftest-filesystems
Tree: cip-gitlab
Branch: ci/iwamatsu/linux-4.19.y-cip-rc
Describe: v4.19.252-cip78-113-gb7034e0f773f8
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: b7034e0f773f811f76bd4c5795f4eafe7e1dede9


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
-------------------------+-------+---------+----------+-----------+------------
r8a774a1-hihope-rzg2m-ex | arm64 | lab-cip | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e4544f0950919f2bdaf0e3

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-cip/kselftest-filesystems-r8a774a1-hihope-rzg2m-ex.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-cip/kselftest-filesystems-r8a774a1-hihope-rzg2m-ex.html
Rootfs: http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20220718.0/arm64/initrd.cpio.gz


* kselftest-filesystems.login: https://kernelci.org/test/case/id/62e4544f0950919f2bdaf0e4
failing since 7 days (last pass: v4.19.249-cip76-57-gef3cc1b9e556, first fail: v4.19.251-cip77-82-g10c370b53152)


cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc baseline: 53 runs, 9 regressions (v4.19.252-cip78-113-gb7034e0f773f8) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/iwamatsu/linux-4.19.y-cip-rc baseline: 53 runs, 9 regressions (v4.19.252-cip78-113-gb7034e0f773f8)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2 | arm64 | lab-broonie | gcc-10 | defconfig | 1
qemu_arm64-virt-gicv2 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv2-uefi | arm64 | lab-broonie | gcc-10 | defconfig | 1
qemu_arm64-virt-gicv2-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig | 1
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv3-uefi | arm64 | lab-broonie | gcc-10 | defconfig | 1
qemu_arm64-virt-gicv3-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
rk3399-gru-kevin | arm64 | lab-collabora | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fiwamatsu%2Flinux-4.19.y-cip-rc/kernel/v4.19.252-cip78-113-gb7034e0f773f8/plan/baseline/

Test: baseline
Tree: cip-gitlab
Branch: ci/iwamatsu/linux-4.19.y-cip-rc
Describe: v4.19.252-cip78-113-gb7034e0f773f8
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: b7034e0f773f811f76bd4c5795f4eafe7e1dede9


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2 | arm64 | lab-broonie | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e4533ddc74fcc975daf07d

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e4533ddc74fcc975daf07e
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e4541811adf991fbdaf072

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e4541811adf991fbdaf073
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2-uefi | arm64 | lab-broonie | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e4533c99162bab62daf072

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e4533c99162bab62daf073
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e454a4143b83c63cdaf071

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e454a4143b83c63cdaf072
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e4533e99162bab62daf078

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e4533e99162bab62daf079
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e454a5ed5011c8efdaf05f

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e454a5ed5011c8efdaf060
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3-uefi | arm64 | lab-broonie | gcc-10 | defconfig | 1

Details: https://kernelci.org/test/plan/id/62e45327dc74fcc975daf05a

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e45327dc74fcc975daf05b
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e454907f1d7e6044daf059

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e454907f1d7e6044daf05a
failing since 72 days (last pass: v4.19.239-cip72-68-g407458469172, first fail: v4.19.242-cip73-50-gd57bc44cb340)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
rk3399-gru-kevin | arm64 | lab-collabora | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e454280950919f2bdaf05c

Results: 83 PASS, 7 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-collabora/baseline-rk3399-gru-kevin.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.252-cip78-113-gb7034e0f773f8/arm64/defconfig+arm64-chromebook/gcc-10/lab-collabora/baseline-rk3399-gru-kevin.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.bootrr.rockchip-i2s1-probed: https://kernelci.org/test/case/id/62e454280950919f2bdaf07e
failing since 138 days (last pass: v4.19.229-cip67-111-g5c3c0b39cf3b, first fail: v4.19.231-cip68-123-g92e3e7f3d4df)

2022-07-29T21:41:48.951430 /lava-6918640/1/../bin/lava-test-case

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