From: Geert Uytterhoeven <geert+renesas@...> The Cortex-A7 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or

From: Geert Uytterhoeven <geert+renesas@...> Fixes: e0d2da54c4d01ba2 ("ARM: dts: r8a7745: add [H]SCIF{|A|B} support") Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by:

From: Marc Zyngier <marc.zyngier@...> Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size

From: Geert Uytterhoeven <geert+renesas@...> Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC "always-on" PM Domain, so it can be power managed using that clock. Note that

From: Sergei Shtylyov <sergei.shtylyov@...> Describe the IRQC interrupt controller in the R8A7745 device tree. Based on the original (and large) patch by Dmitry

From: Sergei Shtylyov <sergei.shtylyov@...> Define the generic R8A7745 part of the Ether device node. Based on the original (and large) patch by Dmitry

From: Biju Das <biju.das@...> Describe [H]SCIF{|A|B} ports in the R8A7745 device tree. Based on the original (and large) patch by Dmitry

From: Sergei Shtylyov <sergei.shtylyov@...> Describe SYS-DMAC0/1 in the R8A7745 device tree. Based on the original (and large) patch by Dmitry

From: Biju Das <biju.das@...> Declare all core clocks and DIV6 clocks, as well as all MSTP clocks. Signed-off-by: Biju Das <biju.das@...> Reviewed-by: Fabrizio Castro

From: Sergei Shtylyov <sergei.shtylyov@...> The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Based on the original

From: Biju Das <biju.das@...> Add macros usable by device tree sources to reference r8a7745 clocks by index. Signed-off-by: Biju Das <biju.das@...> Reviewed-by: Fabrizio Castro

From: Biju Das <biju.das@...> Document r8a7745 MSTP clock support. Signed-off-by: Biju Das <biju.das@...> Reviewed-by: Fabrizio Castro <fabrizio.castro@...> ---

From: Biju Das <biju.das@...> Document r8a7745 CPG DIV6 clock support. Signed-off-by: Biju Das <biju.das@...> Reviewed-by: Fabrizio Castro <fabrizio.castro@...> ---

From: Biju Das <biju.das@...> Document r8a7745 CPG clock support. Signed-off-by: Biju Das <biju.das@...> Reviewed-by: Fabrizio Castro <fabrizio.castro@...> ---

Document the iW-RainboW-G22D device tree bindings. It is just a placeholder for the time being, the actual implementation is not available yet. Signed-off-by: Fabrizio Castro

Document the iW-RainboW-G22M-SM SODIMM System on Module device tree bindings. It is just a placeholder for the time being, the actual implementation is not available yet. Signed-off-by: Fabrizio

From: Biju Das <biju.das@...> RZ/G1E doesn't have the PLL0CR register, but uses a fixed multiplier (depending on mode pins) and divider similar to R-Car E2. Add RZ/G1E to pll0_mult_match

From: Geert Uytterhoeven <geert+renesas@...> R-Car V2H and E2 do not have the PLL0CR register, but use a fixed multiplier (depending on mode pins) and divider. This corrects the clock rate of

From: Benjamin Herrenschmidt <benh@...> This provides an equivalent of of_fdt_match() for non-flat trees. This is more practical than matching an array of of_device_id structs when

From: Geert Uytterhoeven <geert+renesas@...> According to the datasheet, the frequency of the ARM architecture timer on RZ/G1E depends on the frequency of the ZS clock, just like on R-Car E2