From: Sergei Shtylyov <sergei.shtylyov@...> The ATA_AVTP_* signals are documented as reserved in the recent R-Car E2 user's manual (the only remaining mention is in the table 5.2 and I

From: Sergei Shtylyov <sergei.shtylyov@...> The R8A7794 PFC driver was apparently based on the preliminary revisions of the user's manual which called I2C5 device IIC0 and IIC0 device

From: Sergei Shtylyov <sergei.shtylyov@...> All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix

From: Koji Matsuoka <koji.matsuoka.xm@...> r8a7794 PFC DU support from the R-Car Gen2 v1.9.4 BSP [Magnus: added the description, added missing dot clock output signals, separated CDE and

From: Andrey Gusakov <andrey.gusakov@...> GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values are listed instead of 4... [Sergei: fixed up the formatting, renamed,

From: Sergei Shtylyov <sergei.shtylyov@...> Add the EtherAVB pin groups to the R8A7794 PFC driver. Based on the patches by Mitsuhiro Kimura

From: Ryo Kataoka <ryo.kataoka.wt@...> Add the audio clock pin groups to the R8A7794 PFC driver. [Sergei: fixed pin group names to reflect the reality, fixed pin names in the comments to

From: Ryo Kataoka <ryo.kataoka.wt@...> Add the SSI pin groups to the R8A7794 PFC driver. [Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control

From: Geert Uytterhoeven <geert+renesas@...> Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG)

From: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@...> Acked-by: Laurent

From: Biju Das <biju.das@...> Add support for iWave RainboW-G22D-SODIMM board based on RZ/G1E. Signed-off-by: Biju Das <biju.das@...> Signed-off-by: Simon Horman

From: Biju Das <biju.das@...> Add support for iWave RZG1E SODIMM System On Module. http://www.iwavesystems.com/rz-g1e-sodimm-module.html Signed-off-by: Biju Das

From: Geert Uytterhoeven <geert+renesas@...> The Cortex-A7 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or

From: Geert Uytterhoeven <geert+renesas@...> Fixes: e0d2da54c4d01ba2 ("ARM: dts: r8a7745: add [H]SCIF{|A|B} support") Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by:

From: Marc Zyngier <marc.zyngier@...> Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size

From: Geert Uytterhoeven <geert+renesas@...> Link the ARM GIC to the INTC-SYS module clock, and add it to the SYSC "always-on" PM Domain, so it can be power managed using that clock. Note that

From: Sergei Shtylyov <sergei.shtylyov@...> Describe the IRQC interrupt controller in the R8A7745 device tree. Based on the original (and large) patch by Dmitry

From: Sergei Shtylyov <sergei.shtylyov@...> Define the generic R8A7745 part of the Ether device node. Based on the original (and large) patch by Dmitry

From: Biju Das <biju.das@...> Describe [H]SCIF{|A|B} ports in the R8A7745 device tree. Based on the original (and large) patch by Dmitry

From: Sergei Shtylyov <sergei.shtylyov@...> Describe SYS-DMAC0/1 in the R8A7745 device tree. Based on the original (and large) patch by Dmitry