From: Sergei Shtylyov <sergei.shtylyov@...> commit ac142a7fd291f4230923f221a594ce0281a96a72 upstream. Add support for the R-Car gen3 CMT types 0/1 -- they seem to be the same CMT

From: Sergei Shtylyov <sergei.shtylyov@...> commit 9a199422b0d08efaaef2df006c34b0653591a4bf upstream. Document support for the R-Car gen3 CMT types 0/1 bindings -- they seem to be the

From: Sergei Shtylyov <sergei.shtylyov@...> commit eceb4c49aed0fafbc4967e788231b1eba42b7606 upstream. There's no good reason for the sh_cmt_of_table[] initializer to violate the

From: Sergei Shtylyov <sergei.shtylyov@...> commit 37e7742c55ba856eaec7e35673ee370f36eb17f3 upstream. The driver seems to abuse *unsigned long* not only for the (32-bit) register

From: Sergei Shtylyov <sergei.shtylyov@...> commit 22627c6f3ed3d9d0df13eec3c831b08f8186c38e upstream. When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed that

From: Kuninori Morimoto <kuninori.morimoto.gx@...> commit efad01173717b0d0ad8a7dc91cc447f19d8447f3 upstream. This patch updates license to use SPDX-License-Identifier instead of

Dear All, this series backports what's necessary to support CMT and TMU on the RZ/G2E. This series depends on: https://patchwork.kernel.org/project/cip-dev/list/?series=98481 Thanks, Fab Biju Das

Hi Suzuki, OK, then I'd propose having a meeting about this so that I can explain how this variant works and how we make use of it. When do you think you'll come to this point so that a meeting makes

Hi Christian, I understand. Thank you for the explanation. That makes sense. I thought that the A/B update way adopted by meta-swupdate-boards was a little difficult to understand and not very

Hi Suzuki, You're always welcome. That sounds good! Glad I could help here. Sounds reasonable, good to have it sorted out. This is because SWUpdate is designed around a multi-process model

Hello CIP RT Folks! I'm pleased to announce the 4.4.176-cip31-rt23 stable release. This release is just an update to the new stable 4.4.176-cip31 version and no RT specific changes have been

Hi all, Sorry for the spam. The subject got corrupted while sending the patch. Please ignore this patch. I have sent another patch to fix

From: Fabrizio Castro <fabrizio.castro@...> Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@...> Reviewed-by: Geert Uytterhoeven

Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@...> Reviewed-by: Geert Uytterhoeven <geert+renesas@...> Reviewed-by: Simon Horman

From: Biju Das <biju.das@...> This patch enables PCIEC0 PCI express controller on the sub board. Signed-off-by: Biju Das <biju.das@...> Reviewed-by: Geert Uytterhoeven

From: Biju Das <biju.das@...> Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges mapping for pciec0 node. Also declare pcie bus clock, since it is generated on the

This patch adds PCI express channel 0 device tree node to the RZ/G2E (a.k.a. R8A774C0) SoC dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@...> Signed-off-by: Simon Horman

Add PCIe support for the RZ/G2E (a.k.a. R8A774C0). Signed-off-by: Fabrizio Castro <fabrizio.castro@...> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@...> Reviewed-by: Geert

Dear All, This series adds PCIe support to the EK874 board. Thanks, Fab Biju Das (2): arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support arm64: dts: renesas: cat875: Enable PCIe

Hi, Although not automated yet, I created a page in gitlab wiki.I need to learn API of gitlab... https://gitlab.com/cip-project/cip-kernel/lts-commit-list/wikis/Review-linux-4.4.y Best regards,