|
|
[PATCH 4.19.y-cip 13/23] clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
From: Simon Horman <horms+renesas@...>
commit e0836e36384321ab1b4af05ab441c0c59a972596 upstream.
After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have
|
From: Simon Horman <horms+renesas@...>
commit e0836e36384321ab1b4af05ab441c0c59a972596 upstream.
After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have
|
By
Biju Das <biju.das@...>
·
#2627
·
|
|
[PATCH 4.19.y-cip 12/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
commit 10d9ea5100c89afd677a202036e0e34e129a6c52 upstream.
Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.
This is in preparation for supporting the Z2 clock
|
commit 10d9ea5100c89afd677a202036e0e34e129a6c52 upstream.
Parameterise the offset of control bits within the FRQCRC register
for Z and Z2 clocks.
This is in preparation for supporting the Z2 clock
|
By
Biju Das <biju.das@...>
·
#2626
·
|
|
[PATCH 4.19.y-cip 11/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
commit 20cc05ba04a93f05d6c50789fe35d762a2db4e96 upstream.
Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to
|
commit 20cc05ba04a93f05d6c50789fe35d762a2db4e96 upstream.
Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to
|
By
Biju Das <biju.das@...>
·
#2625
·
|
|
[PATCH 4.19.y-cip 10/23] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
From: Geert Uytterhoeven <geert+renesas@...>
commit 6a82559f745bc26d2e4974c1d26014ef7fa14794 upstream.
Explicitly pass the clock's name and register offset to
cpg_sd_clk_register(), so the
|
From: Geert Uytterhoeven <geert+renesas@...>
commit 6a82559f745bc26d2e4974c1d26014ef7fa14794 upstream.
Explicitly pass the clock's name and register offset to
cpg_sd_clk_register(), so the
|
By
Biju Das <biju.das@...>
·
#2624
·
|
|
[PATCH 4.19.y-cip 09/23] clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK
From: Fabrizio Castro <fabrizio.castro@...>
commit df446f7e6ec0ed474dab2e6f19e4618116907f29 upstream.
Enum LAST_DT_CORE_CLK needs updating as R8A774A1_CLK_CANFD
was recently added and
|
From: Fabrizio Castro <fabrizio.castro@...>
commit df446f7e6ec0ed474dab2e6f19e4618116907f29 upstream.
Enum LAST_DT_CORE_CLK needs updating as R8A774A1_CLK_CANFD
was recently added and
|
By
Biju Das <biju.das@...>
·
#2623
·
|
|
[PATCH 4.19.y-cip 08/23] clk: renesas: rcar-gen3: Add spinlock
From: Sergei Shtylyov <sergei.shtylyov@...>
commit 875e8f6b0156c0ad56fd0c29c78e3f2f67ec0b16 upstream.
Protect the CPG register read-modify-write sequence with a
|
From: Sergei Shtylyov <sergei.shtylyov@...>
commit 875e8f6b0156c0ad56fd0c29c78e3f2f67ec0b16 upstream.
Protect the CPG register read-modify-write sequence with a
|
By
Biju Das <biju.das@...>
·
#2622
·
|
|
[PATCH 4.19.y-cip 07/23] clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
From: Sergei Shtylyov <sergei.shtylyov@...>
commit 8cb8f16c62e5ea9c77ca7d25af761f4eaea670ba upstream.
There's quite often repeated sequence of a CPG register read-modify-write,
so it
|
From: Sergei Shtylyov <sergei.shtylyov@...>
commit 8cb8f16c62e5ea9c77ca7d25af761f4eaea670ba upstream.
There's quite often repeated sequence of a CPG register read-modify-write,
so it
|
By
Biju Das <biju.das@...>
·
#2621
·
|
|
[PATCH 4.19.y-cip 06/23] clk: renesas: r8a774a1: Add missing CANFD clock
From: Fabrizio Castro <fabrizio.castro@...>
commit 9d034e151b407cbd2c66bc4c48b423f814533374 upstream.
This patch adds the missing CANFD clock to the r8a774a1 specific
clock
|
From: Fabrizio Castro <fabrizio.castro@...>
commit 9d034e151b407cbd2c66bc4c48b423f814533374 upstream.
This patch adds the missing CANFD clock to the r8a774a1 specific
clock
|
By
Biju Das <biju.das@...>
·
#2620
·
|
|
[PATCH 4.19.y-cip 05/23] clk: renesas: Remove usage of CLK_IS_BASIC
From: Stephen Boyd <sboyd@...>
commit ddbae6658d4dc495ac62f7977062b33bb15d1af6 upstream.
This flag doesn't look to be used by any code, just set in various clk
init structures and then never
|
From: Stephen Boyd <sboyd@...>
commit ddbae6658d4dc495ac62f7977062b33bb15d1af6 upstream.
This flag doesn't look to be used by any code, just set in various clk
init structures and then never
|
By
Biju Das <biju.das@...>
·
#2619
·
|
|
[PATCH 4.19.y-cip 04/23] clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
From: Niklas Söderlund <niklas.soderlund+renesas@...>
commit 36c4da4f552a126bb29a95dc5c9608795491e32a upstream.
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for
|
From: Niklas Söderlund <niklas.soderlund+renesas@...>
commit 36c4da4f552a126bb29a95dc5c9608795491e32a upstream.
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for
|
By
Biju Das <biju.das@...>
·
#2618
·
|
|
[PATCH 4.19.y-cip 03/23] clk: renesas: rcar-gen3: Add documentation for SD clocks
From: Niklas Söderlund <niklas.soderlund+renesas@...>
commit e2f4dd1f5b51b4dab813aa6e4db44e87aa750393 upstream.
Document the known use cases of the different clock settings. This is
useful
|
From: Niklas Söderlund <niklas.soderlund+renesas@...>
commit e2f4dd1f5b51b4dab813aa6e4db44e87aa750393 upstream.
Document the known use cases of the different clock settings. This is
useful
|
By
Biju Das <biju.das@...>
·
#2617
·
|
|
[PATCH 4.19.y-cip 02/23] clk: renesas: rcar-gen3: Set state when registering SD clocks
From: Niklas Söderlund <niklas.soderlund+renesas@...>
commit ecda0a09fa9933bcd67e33c952f778f0872392ed upstream.
The driver tries to figure out which state a SD clock is in when the
clock
|
From: Niklas Söderlund <niklas.soderlund+renesas@...>
commit ecda0a09fa9933bcd67e33c952f778f0872392ed upstream.
The driver tries to figure out which state a SD clock is in when the
clock
|
By
Biju Das <biju.das@...>
·
#2616
·
|
|
[PATCH 4.19.y-cip 01/23] clk: renesas: r8a774a1: Add CPEX clock
From: Geert Uytterhoeven <geert+renesas@...>
commit f845b01d478a4d139fe3493f1e6ec8d9110ce56c upstream.
Implement support for the CPEX clock on RZ/G2M. This clock can be
selected as a clock
|
From: Geert Uytterhoeven <geert+renesas@...>
commit f845b01d478a4d139fe3493f1e6ec8d9110ce56c upstream.
Implement support for the CPEX clock on RZ/G2M. This clock can be
selected as a clock
|
By
Biju Das <biju.das@...>
·
#2615
·
|
|
[PATCH 4.19.y-cip 00/23] Clock enhancements
This patch series add OPP tables,HS400 quirk for SD clock,
add support Z2 clock and fix some of parent clocks.
This patch series is based on linux-4.19.y-cip and all the patches
in this series are
|
This patch series add OPP tables,HS400 quirk for SD clock,
add support Z2 clock and fix some of parent clocks.
This patch series is based on linux-4.19.y-cip and all the patches
in this series are
|
By
Biju Das <biju.das@...>
·
#2614
·
|
|
Re: [ANNOUNCE] 4.4.176-cip31-rt23
Hi!
I'm looking into it. I have -rt-rebase based on
v4.4.179-rt181-cip34-rebase (close to what you want but not quite
there; I can publish it if it would be useful), but duplicating same
result with
|
Hi!
I'm looking into it. I have -rt-rebase based on
v4.4.179-rt181-cip34-rebase (close to what you want but not quite
there; I can publish it if it would be useful), but duplicating same
result with
|
By
Pavel Machek
·
#2613
·
|
|
Re: RT testing
Hi!
(List added to the cc).
Thanks for all the help!
I got -cip-rt kernel to work on EBV Socrates, and it seems to be
suitable machine for testing. Latencies are under 70 usec under normal
loads.
|
Hi!
(List added to the cc).
Thanks for all the help!
I got -cip-rt kernel to work on EBV Socrates, and it seems to be
suitable machine for testing. Latencies are under 70 usec under normal
loads.
|
By
Pavel Machek
·
#2612
·
|
|
Re: Regarding backporting RTC PCF85263 driver to cip 4.4 kernel
Hi Nobuhiro,
Thanks for the feedback.
.feghali.xb@...>; cip-
OK. Will send patch based on option 2.
Regards,
Biju
|
Hi Nobuhiro,
Thanks for the feedback.
.feghali.xb@...>; cip-
OK. Will send patch based on option 2.
Regards,
Biju
|
By
Biju Das <biju.das@...>
·
#2611
·
|
|
Re: Regarding backporting RTC PCF85263 driver to cip 4.4 kernel
Hi Pavel,
Thanks for the feedback.
Ok. I will send patch based on option 2.
Regards,
Biju
|
Hi Pavel,
Thanks for the feedback.
Ok. I will send patch based on option 2.
Regards,
Biju
|
By
Biju Das <biju.das@...>
·
#2610
·
|
|
Re: Regarding backporting RTC PCF85263 driver to cip 4.4 kernel
Hi,
By
Nobuhiro Iwamatsu
·
#2609
·
|
|
Re: Request for guidance: removal of old config files [was: Kernel configurations for 4.19?]
Hi Ben,
By
Nobuhiro Iwamatsu
·
#2608
·
|
