|
|
Re: [PATCH 4.19.y-cip 00/39] Add RZ/G2N SYSC/RST/Clock/PFC support
Hi!
I have made two comments on the patches, but I believe the series is
good enough to merge.
I'll do that later if there are no objections.
Best regards,
Pavel
--
DENX Software
|
Hi!
I have made two comments on the patches, but I believe the series is
good enough to merge.
I'll do that later if there are no objections.
Best regards,
Pavel
--
DENX Software
|
By
Pavel Machek
·
#4082
·
|
|
Re: [PATCH 4.19.y-cip 08/39] soc: renesas: r8a7795-sysc: Fix power request conflicts
Hi!
So you are storing bitfield in the pointer, ok.
But now you do strange dance with types. I'd understand quirks being
unsigned long (because that's same size as void *). I also could
understand
|
Hi!
So you are storing bitfield in the pointer, ok.
But now you do strange dance with types. I'd understand quirks being
unsigned long (because that's same size as void *). I also could
understand
|
By
Pavel Machek
·
#4081
·
|
|
Re: [PATCH 4.19.y-cip 03/39] soc: renesas: Add Renesas R8A774B1 config option
Hi!
Normally, config option should be close to the end of the series
(having it in the begining can be surprising during the bisect, for
example).
Best regards,
Pavel
--
DENX Software
|
Hi!
Normally, config option should be close to the end of the series
(having it in the begining can be surprising during the bisect, for
example).
Best regards,
Pavel
--
DENX Software
|
By
Pavel Machek
·
#4080
·
|
|
[PATCH 4.19.y-cip 39/39] arm64: defconfig: Enable R8A774B1 SoC
commit d8b178741e5ba571fbcc187c9e3cf9c0eaebf328 upstream.
Enable the Renesas RZ/G2N (R8A774B1) SoC in the ARM64 defconfig.
Signed-off-by: Biju Das <biju.das@...>
Link:
|
commit d8b178741e5ba571fbcc187c9e3cf9c0eaebf328 upstream.
Enable the Renesas RZ/G2N (R8A774B1) SoC in the ARM64 defconfig.
Signed-off-by: Biju Das <biju.das@...>
Link:
|
By
Biju Das <biju.das@...>
·
#4079
·
|
|
[PATCH 4.19.y-cip 38/39] arm64: dts: renesas: Add HiHope RZ/G2N main board support
commit 83f7f812a8706aa9c23b02d945f670cdef116e2c upstream.
Basic support for the HiHope RZ/G2N main board:
- Memory,
- Main crystal,
- Serial console
Signed-off-by: Biju Das
|
commit 83f7f812a8706aa9c23b02d945f670cdef116e2c upstream.
Basic support for the HiHope RZ/G2N main board:
- Memory,
- Main crystal,
- Serial console
Signed-off-by: Biju Das
|
By
Biju Das <biju.das@...>
·
#4078
·
|
|
[PATCH 4.19.y-cip 37/39] arm64: dts: renesas: Initial r8a774b1 SoC device tree
commit 9b33e3001b67f9dcd52548db2949f5a04d0b4017 upstream.
Basic support for the RZ/G2N (R8A774B1) SoC. Added placeholders
to avoid compilation error with the common platform code.
Signed-off-by:
|
commit 9b33e3001b67f9dcd52548db2949f5a04d0b4017 upstream.
Basic support for the RZ/G2N (R8A774B1) SoC. Added placeholders
to avoid compilation error with the common platform code.
Signed-off-by:
|
By
Biju Das <biju.das@...>
·
#4077
·
|
|
[PATCH 4.19.y-cip 36/39] dt-bindings: serial: sh-sci: Document r8a774b1 bindings
commit fc5f3782da3c73bbbe2293551219b2ded0660357 upstream.
RZ/G2N (R8A774B1) SoC also has the R-Car Gen3 compatible SCIF and
HSCIF ports, so document the SoC specific bindings.
Signed-off-by: Biju
|
commit fc5f3782da3c73bbbe2293551219b2ded0660357 upstream.
RZ/G2N (R8A774B1) SoC also has the R-Car Gen3 compatible SCIF and
HSCIF ports, so document the SoC specific bindings.
Signed-off-by: Biju
|
By
Biju Das <biju.das@...>
·
#4076
·
|
|
[PATCH 4.19.y-cip 35/39] pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3
From: Keiya Nobuta <nobuta.keiya@...>
commit f846d1e704f2d07a7f359f65eac2c8cac565db35 upstream.
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.
Signed-off-by: Keiya Nobuta
|
From: Keiya Nobuta <nobuta.keiya@...>
commit f846d1e704f2d07a7f359f65eac2c8cac565db35 upstream.
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.
Signed-off-by: Keiya Nobuta
|
By
Biju Das <biju.das@...>
·
#4075
·
|
|
[PATCH 4.19.y-cip 34/39] pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC support
commit 271ff378a30086952eb9df1471006dff9a6b5f92 upstream.
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965),
however it doesn't have several automotive specific peripherals.
|
commit 271ff378a30086952eb9df1471006dff9a6b5f92 upstream.
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965),
however it doesn't have several automotive specific peripherals.
|
By
Biju Das <biju.das@...>
·
#4074
·
|
|
[PATCH 4.19.y-cip 33/39] dt-bindings: pinctrl: sh-pfc: Document r8a774b1 PFC support
commit 887047c317a48e49de7d0e0318ec0464666f6229 upstream.
Document PFC support for the R8A774B1 SoC.
Signed-off-by: Biju Das <biju.das@...>
Link:
|
commit 887047c317a48e49de7d0e0318ec0464666f6229 upstream.
Document PFC support for the R8A774B1 SoC.
Signed-off-by: Biju Das <biju.das@...>
Link:
|
By
Biju Das <biju.das@...>
·
#4073
·
|
|
[PATCH 4.19.y-cip 32/39] pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pins
From: Geert Uytterhoeven <geert+renesas@...>
commit 5da89cedce5c5b9d728b334c0183211fbe2ddd0b upstream.
Update the R-Car M3-N pin control driver to use the new macros for
describing pins
|
From: Geert Uytterhoeven <geert+renesas@...>
commit 5da89cedce5c5b9d728b334c0183211fbe2ddd0b upstream.
Update the R-Car M3-N pin control driver to use the new macros for
describing pins
|
By
Biju Das <biju.das@...>
·
#4072
·
|
|
[PATCH 4.19.y-cip 31/39] pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functions
From: Geert Uytterhoeven <geert+renesas@...>
commit be1c072d66282b4633239b8a74432cf3a95d5b22 upstream.
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-N
|
From: Geert Uytterhoeven <geert+renesas@...>
commit be1c072d66282b4633239b8a74432cf3a95d5b22 upstream.
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-N
|
By
Biju Das <biju.das@...>
·
#4071
·
|
|
[PATCH 4.19.y-cip 30/39] pinctrl: sh-pfc: r8a77965: Add I2C{0, 3, 5} pins, groups and functions
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 0a042b355e60269ad30725b5b5ca68fc5371a8df upstream.
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins
|
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 0a042b355e60269ad30725b5b5ca68fc5371a8df upstream.
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins
|
By
Biju Das <biju.das@...>
·
#4070
·
|
|
[PATCH 4.19.y-cip 29/39] pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 79dbbdbeccc6784d5e189710adcca750c03d3bd4 upstream.
This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77965
SoC.
Based on
|
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 79dbbdbeccc6784d5e189710adcca750c03d3bd4 upstream.
This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77965
SoC.
Based on
|
By
Biju Das <biju.das@...>
·
#4069
·
|
|
[PATCH 4.19.y-cip 28/39] pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 729257d674bc2e68bf051af5c7202d882bccafe0 upstream.
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A77965
|
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 729257d674bc2e68bf051af5c7202d882bccafe0 upstream.
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A77965
|
By
Biju Das <biju.das@...>
·
#4068
·
|
|
[PATCH 4.19.y-cip 27/39] pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
From: Geert Uytterhoeven <geert+renesas@...>
commit 86c045c2e4201e94ef37458e5777fcb2dab33a11 upstream.
Unlike R-Car M3-W, R-Car M3-N does not have DU_DOTCLKIN2, but the
corresponding pin
|
From: Geert Uytterhoeven <geert+renesas@...>
commit 86c045c2e4201e94ef37458e5777fcb2dab33a11 upstream.
Unlike R-Car M3-W, R-Car M3-N does not have DU_DOTCLKIN2, but the
corresponding pin
|
By
Biju Das <biju.das@...>
·
#4067
·
|
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[PATCH 4.19.y-cip 26/39] pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functions
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 1b259dde9bd9001783d2deb1c4773a2e5ce45860 upstream.
This patch adds CAN FD{0,1} pins, groups and functions to the
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From: Takeshi Kihara <takeshi.kihara.df@...>
commit 1b259dde9bd9001783d2deb1c4773a2e5ce45860 upstream.
This patch adds CAN FD{0,1} pins, groups and functions to the
|
By
Biju Das <biju.das@...>
·
#4066
·
|
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[PATCH 4.19.y-cip 25/39] pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functions
From: Takeshi Kihara <takeshi.kihara.df@...>
commit 3a44d6a92e2572c602cfce692ae96d0e95d9c848 upstream.
This patch adds CAN{0,1} pins, groups and functions to the R8A77965
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From: Takeshi Kihara <takeshi.kihara.df@...>
commit 3a44d6a92e2572c602cfce692ae96d0e95d9c848 upstream.
This patch adds CAN{0,1} pins, groups and functions to the R8A77965
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By
Biju Das <biju.das@...>
·
#4065
·
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[PATCH 4.19.y-cip 24/39] pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions
From: Jacopo Mondi <jacopo+renesas@...>
commit 270b6eb715573c0d05b75351f804b7b445d88d4b upstream
The VIN4 and VIN5 interfaces support parallel video input.
Add pin, mux and functions
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From: Jacopo Mondi <jacopo+renesas@...>
commit 270b6eb715573c0d05b75351f804b7b445d88d4b upstream
The VIN4 and VIN5 interfaces support parallel video input.
Add pin, mux and functions
|
By
Biju Das <biju.das@...>
·
#4064
·
|
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[PATCH 4.19.y-cip 23/39] pinctrl: sh-pfc: r8a77965: Add Audio SSI pin support
From: Hoan Nguyen An <na-hoan@...>
commit 7a7dfc4770c7904062186ff480af59a68c858ca0 upstream.
Add Audio SSI pin support for r8a77965.
Signed-off-by: Hoan Nguyen An
|
From: Hoan Nguyen An <na-hoan@...>
commit 7a7dfc4770c7904062186ff480af59a68c858ca0 upstream.
Add Audio SSI pin support for r8a77965.
Signed-off-by: Hoan Nguyen An
|
By
Biju Das <biju.das@...>
·
#4063
·
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