Hi! I quickly reviewed the patches, and might have minor comments, but the series look good. Tests are currently running

From: Yoshihiro Kaneko <ykaneko0929@...> commit 63a0f811558b9a5587a8c52978a57a8b528b074a upstream. Sort nodes. If node address is present * Sort by node address, grouping all nodes with

From: Magnus Damm <damm+renesas@...> commit b31b43c92daee8628c60b411452b1b17acdac580 upstream. Convert bootargs from ip=dhcp to ip=on Signed-off-by: Magnus Damm

From: Fabrizio Castro <fabrizio.castro@...> commit 7fc009cbd7d11d6b27ba5443dbfa80a0513829e4 upstream. Power rail "D12.0V" comes straight from the power barrel connector, and it's used in

From: Jacopo Mondi <jacopo+renesas@...> commit 38290431d56d7d3928ac89e9f8d3d6b3c8df4c6e upstream. Update the 'vsps' property in the R-Car Gen3 SoC device tree files to match what's in the

From: Geert Uytterhoeven <geert+renesas@...> commit 23ad2b4672a7572e0f091cfe90aac1cd9bdca28a upstream. Since the R8A774C0 SoC uses DU{0,1} only, the register block length should be

From: Fabrizio Castro <fabrizio.castro@...> commit e8efd2a8e20a9d7a7bd701950254a0ae04a8ce27 upstream. Define "assigned-clocks" and "assigned-clock-rates" properties for CAN[01] DT nodes,

From: Robin Murphy <robin.murphy@...> commit 11290c09e29600f45684113d78209d1df1c22aba upstream. Apparently this DTS crossed over with commit 31af04cd60d3 ("arm64: dts: Remove inconsistent use of

From: Biju Das <biju.das@...> commit 652fd0f44e98a7fa87be9e97115749e103ccf703 upstream. Describe the dynamic power coefficient of A53 CPUs. Based on work by Gaku Inami

From: Biju Das <biju.das@...> commit 8438bfda9d76815707a7823ab91a944eea6d6266 upstream. Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to

From: Yoshihiro Kaneko <ykaneko0929@...> commit 20386f0d84a22214d1f037dedfffb6709dd0117a upstream. Update calculation for the R-Car Gen3 and RZ/G2 SoCs which have a thermal IP block controlled

From: Fabrizio Castro <fabrizio.castro@...> commit 8cb7ec14188649cf2151464050413e2814fd7cf1 upstream. Add missing RZ/G2[EM] CANFD clock specific documentation. Fixes: 868b7c0f43e61f22

From: Eugeniu Rosca <rosca.eugeniu@...> commit 4f145f14f6b98b5aa0dd91bdae518b3f24f74b37 upstream. Document the support for rcar_can on R8A77965 SoC devices. Add R8A77965 to the list of SoCs

This patch series intends to do the following: 1: Add IPA support 2: Update the CAN bindings 3: Fix display node range 4: Minor tweaks for sorting the nodes 5: Use any protocol available in kernel for

Hi! Even basic cyclictest is good to have, but it would be really good to have some kind of background load. I'd expect latency to raise by factor of 3 in make -j 5 of kernel. I tried to come up

Hello Daniel, Not a bad idea. I'll give it a go. Do you have an 'RT' config fragment you can share? I guess it depends on what approach the Kernel maintainers would rather take. Maintainers: Do we

Hello Daniel, Thank you for the information. Relieved to know that no dependency on specific python version :) Thanks, Kazu

Hello, Okay. I'm thinking that we aren't going to be able to escape having a separate 'testing' version of CIP-Core, based on ISAR on the assumption that it has more supported packages then Deby. Or

Hi Chris, Welcome on board :) I am using merge_config.sh to build the configuration. There are some catches but generally it works good. I've hacked a small tool for automization around it. With

Hi, cyclictest.sh uses automated/lib/parse_rt_tests_results.py to parse the results. The python code runs with either Python2 or Python3 $ python3 -m py_compile