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[PATCH 5.10.y-cip 13/24] arm64: dts: renesas: r9a07g044: Add SYSC node
commit 42bbd003910906229cb1dc0eaa812d9cc59e4c77 upstream.
Add SYSC node to RZ/G2L (R9A07G044) SoC .dtsi.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Biju Das
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commit 42bbd003910906229cb1dc0eaa812d9cc59e4c77 upstream.
Add SYSC node to RZ/G2L (R9A07G044) SoC .dtsi.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Biju Das
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By
Lad Prabhakar
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#7136
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[PATCH 5.10.y-cip 12/24] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
commit 690ea5d394eb370973ffcb9ecda6a1855fe87d01 upstream.
Add basic support for RZ/G2L SMARC EVK (based on R9A07G044L2):
- memory
- External input clock
- SCIF
Signed-off-by: Lad Prabhakar
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commit 690ea5d394eb370973ffcb9ecda6a1855fe87d01 upstream.
Add basic support for RZ/G2L SMARC EVK (based on R9A07G044L2):
- memory
- External input clock
- SCIF
Signed-off-by: Lad Prabhakar
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By
Lad Prabhakar
·
#7135
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[PATCH 5.10.y-cip 11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's
commit 68a45525297b2e9afbd9bba807ddd2c9f69beee6 upstream.
Add initial DTSI for RZ/G2{L,LC} SoC's.
File structure:
r9a07g044.dtsi => RZ/G2L family SoC common parts
r9a07g044l1.dtsi => RZ/G2L
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commit 68a45525297b2e9afbd9bba807ddd2c9f69beee6 upstream.
Add initial DTSI for RZ/G2{L,LC} SoC's.
File structure:
r9a07g044.dtsi => RZ/G2L family SoC common parts
r9a07g044l1.dtsi => RZ/G2L
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By
Lad Prabhakar
·
#7134
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[PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l: Add multi clock PM support
From: Biju Das <biju.das.jz@...>
commit 2fa9fd69b3ee015a873e44f7c645ad7bcb79d290 upstream.
Add multi clock PM support for cpg driver.
Signed-off-by: Biju Das
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From: Biju Das <biju.das.jz@...>
commit 2fa9fd69b3ee015a873e44f7c645ad7bcb79d290 upstream.
Add multi clock PM support for cpg driver.
Signed-off-by: Biju Das
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By
Lad Prabhakar
·
#7133
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[PATCH 5.10.y-cip 09/24] clk: renesas: r9a07g044: Add P2 Clock support
From: Biju Das <biju.das.jz@...>
commit 668756f7299d2d3c75add17cb415717e247450ef upstream.
Add support for P2 clock which is sourced from pll3_div2_4_2.
Signed-off-by: Biju Das
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From: Biju Das <biju.das.jz@...>
commit 668756f7299d2d3c75add17cb415717e247450ef upstream.
Add support for P2 clock which is sourced from pll3_div2_4_2.
Signed-off-by: Biju Das
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By
Lad Prabhakar
·
#7132
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[PATCH 5.10.y-cip 08/24] clk: renesas: r9a07g044: Fix P1 Clock
From: Biju Das <biju.das.jz@...>
commit fd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a upstream.
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions
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From: Biju Das <biju.das.jz@...>
commit fd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a upstream.
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions
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By
Lad Prabhakar
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#7131
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[PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Rename divider table
From: Biju Das <biju.das.jz@...>
commit e93c1373613fb2f3e59db5f13271f155820e6a67 upstream.
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares
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From: Biju Das <biju.das.jz@...>
commit e93c1373613fb2f3e59db5f13271f155820e6a67 upstream.
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares
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By
Lad Prabhakar
·
#7130
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[PATCH 5.10.y-cip 06/24] clk: renesas: Add support for R9A07G044 SoC
commit 17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5 upstream.
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.
Based on a patch in the BSP by Binh
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commit 17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5 upstream.
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.
Based on a patch in the BSP by Binh
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By
Lad Prabhakar
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#7129
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[PATCH 5.10.y-cip 05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC
commit ef3c613ccd68a78727b817c3dacf4a68d1ffc67f upstream.
Add CPG core wrapper for RZ/G2L family.
Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@...>.
Signed-off-by: Lad
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commit ef3c613ccd68a78727b817c3dacf4a68d1ffc67f upstream.
Add CPG core wrapper for RZ/G2L family.
Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@...>.
Signed-off-by: Lad
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By
Lad Prabhakar
·
#7128
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[PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC
From: Biju Das <biju.das.jz@...>
commit 3b2cd60689fa439481f535ee4463fb223a276f43 upstream.
Add serial support for RZ/G2L SoC with earlycon and
extended mode register
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From: Biju Das <biju.das.jz@...>
commit 3b2cd60689fa439481f535ee4463fb223a276f43 upstream.
Add serial support for RZ/G2L SoC with earlycon and
extended mode register
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By
Lad Prabhakar
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#7127
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[PATCH 5.10.y-cip 04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
commit 403921373799a133e41b59cb730e2c4239663f51 upstream.
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs, as listed in Table 8.3 ("Clock List")
of the RZ/G2L
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commit 403921373799a133e41b59cb730e2c4239663f51 upstream.
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs, as listed in Table 8.3 ("Clock List")
of the RZ/G2L
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By
Lad Prabhakar
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#7126
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[PATCH 5.10.y-cip 03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
commit f8ec89126a72b399e63399d8d21fd413f4059f00 upstream.
Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in
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commit f8ec89126a72b399e63399d8d21fd413f4059f00 upstream.
Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in
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By
Lad Prabhakar
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#7125
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[PATCH 5.10.y-cip 01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings
commit 92e06e12212abe4b27ff18445a0f88e6b5236331 upstream.
Document R9A07G044 SoC variants, common compatiable string
"renesas,scif-r9a07g044" is added for RZ/G2L and RZ/G2LC SoC.
Signed-off-by: Lad
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commit 92e06e12212abe4b27ff18445a0f88e6b5236331 upstream.
Document R9A07G044 SoC variants, common compatiable string
"renesas,scif-r9a07g044" is added for RZ/G2L and RZ/G2LC SoC.
Signed-off-by: Lad
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By
Lad Prabhakar
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#7124
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[PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK
Hi All,
This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
- CPU
- CPG
- GIC
* Initial device tree for RZ/G2L SMARC EVK
- memory
- External
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Hi All,
This patch series adds the following:
* Serial support
* Clock support
* Initial RZ/G2L SoC DTSI
- CPU
- CPG
- GIC
* Initial device tree for RZ/G2L SMARC EVK
- memory
- External
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By
Lad Prabhakar
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#7123
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cip/linux-5.10.y-cip baseline: 137 runs, 1 regressions (v5.10.83-cip1-7-geb3270fae08d)
#kernelci
cip/linux-5.10.y-cip baseline: 137 runs, 1 regressions (v5.10.83-cip1-7-geb3270fae08d)
Regressions Summary
-------------------
platform | arch | lab | compiler |
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cip/linux-5.10.y-cip baseline: 137 runs, 1 regressions (v5.10.83-cip1-7-geb3270fae08d)
Regressions Summary
-------------------
platform | arch | lab | compiler |
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By
kernelci.org bot <bot@...>
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#7122
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cip/linux-5.10.y-cip build: 175 builds: 3 failed, 172 passed, 4 errors, 10 warnings (v5.10.83-cip1-7-geb3270fae08d)
#kernelci
cip/linux-5.10.y-cip build: 175 builds: 3 failed, 172 passed, 4 errors, 10 warnings (v5.10.83-cip1-7-geb3270fae08d)
Full Build Summary:
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cip/linux-5.10.y-cip build: 175 builds: 3 failed, 172 passed, 4 errors, 10 warnings (v5.10.83-cip1-7-geb3270fae08d)
Full Build Summary:
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By
kernelci.org bot <bot@...>
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#7121
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Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Hello,
We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure.
If the board is not accepted as a CIP reference board, we would still
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Hello,
We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure.
If the board is not accepted as a CIP reference board, we would still
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By
Chris Paterson
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#7120
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Re: CIP IRC weekly meeting today on libera.chat
Hi Jan,
I may not be able to attend today for personal reason.
So, I'll email my work this week.
* I released v4.19.220-cip63 and v4.4.294-cip66
* I reviewed 5.10.85.
* I reviewed patches for
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Hi Jan,
I may not be able to attend today for personal reason.
So, I'll email my work this week.
* I released v4.19.220-cip63 and v4.4.294-cip66
* I reviewed 5.10.85.
* I reviewed patches for
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By
Nobuhiro Iwamatsu
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#7119
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Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Hi!
Looks good to me too. I have series ready due to testing, so I'll push
it.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
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Hi!
Looks good to me too. I have series ready due to testing, so I'll push
it.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
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By
Pavel Machek
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#7118
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Re: New CVE entries in this week
Hi!
This one is actually quite interesting.
Untrusted users should not normally have shell access on embedded
systems, but it highlights topic of coredumps. Default config of
coredumping is
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Hi!
This one is actually quite interesting.
Untrusted users should not normally have shell access on embedded
systems, but it highlights topic of coredumps. Default config of
coredumping is
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By
Pavel Machek
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#7117
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