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[PATCH 5.10.y-cip 20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
commit f91c4c74796acca0a5a3bde747948a844eb2c30b upstream.
Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2):
- memory
- External input clock
- CPG
- Pin controller
- SCIF
-
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commit f91c4c74796acca0a5a3bde747948a844eb2c30b upstream.
Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2):
- memory
- External input clock
- CPG
- Pin controller
- SCIF
-
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By
Biju Das
·
#9017
·
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[PATCH 5.10.y-cip 19/24] arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
commit 7c2b8198f4f321df03e285a931fab2a33668c88d upstream.
The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only
difference being that the RZ/V2L SoC has additional DRP-AI IP
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commit 7c2b8198f4f321df03e285a931fab2a33668c88d upstream.
The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only
difference being that the RZ/V2L SoC has additional DRP-AI IP
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By
Biju Das
·
#9016
·
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[PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC
commit 654f89f9496db716c4e9a79c3c6193d57cfaa963 upstream.
Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet
Interface is identical to one found on the RZ/G2L SoC. No driver
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commit 654f89f9496db716c4e9a79c3c6193d57cfaa963 upstream.
Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet
Interface is identical to one found on the RZ/G2L SoC. No driver
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By
Biju Das
·
#9015
·
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[PATCH 5.10.y-cip 17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register()
commit 2e08ab0427fe3e33a92a37cfe3b6db340ab7397f upstream.
Update rzg2l_gpio_register() to use driver data for chip->names
and check for gpio-range. This allows reusing the driver for
SoC's with
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commit 2e08ab0427fe3e33a92a37cfe3b6db340ab7397f upstream.
Update rzg2l_gpio_register() to use driver data for chip->names
and check for gpio-range. This allows reusing the driver for
SoC's with
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By
Biju Das
·
#9014
·
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[PATCH 5.10.y-cip 16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled
commit 0c8fce49f24e7c8ee2bdff4761f414ad59bfa29a upstream.
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin
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commit 0c8fce49f24e7c8ee2bdff4761f414ad59bfa29a upstream.
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin
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By
Biju Das
·
#9013
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[PATCH 5.10.y-cip 15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl
commit c07b19de2f7ac91662aa99767815a258da6ef16f upstream.
Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package-
and pin-compatible with RZ/G2L. No driver changes are required as
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commit c07b19de2f7ac91662aa99767815a258da6ef16f upstream.
Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package-
and pin-compatible with RZ/G2L. No driver changes are required as
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By
Biju Das
·
#9012
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[PATCH 5.10.y-cip 14/24] dt-bindings: serial: renesas,sci: Document RZ/V2L SoC
commit a359101c7c6404d917a19d52133305ea284a0197 upstream.
Add SCI binding documentation for Renesas RZ/V2L SoC. No driver changes
are required as generic compatible string "renesas,sci" will be used
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commit a359101c7c6404d917a19d52133305ea284a0197 upstream.
Add SCI binding documentation for Renesas RZ/V2L SoC. No driver changes
are required as generic compatible string "renesas,sci" will be used
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By
Biju Das
·
#9011
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[PATCH 5.10.y-cip 13/24] dt-bindings: serial: renesas,scif: Document RZ/V2L SoC
commit b0c86a6083229db0518e2754b2b6298e40e8d637 upstream.
Add SCIF binding documentation for Renesas RZ/V2L SoC. SCIF block on RZ/V2L
is identical to one found on the RZ/G2L SoC. No driver changes
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commit b0c86a6083229db0518e2754b2b6298e40e8d637 upstream.
Add SCIF binding documentation for Renesas RZ/V2L SoC. SCIF block on RZ/V2L
is identical to one found on the RZ/G2L SoC. No driver changes
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By
Biju Das
·
#9010
·
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[PATCH 5.10.y-cip 12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic
From: Geert Uytterhoeven <geert+renesas@...>
commit 29db30c45f07c929c86c40a5b85f18b69c89c638 upstream.
"a * (1 << b)" == "a << b".
No change in generated code.
Signed-off-by: Geert
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From: Geert Uytterhoeven <geert+renesas@...>
commit 29db30c45f07c929c86c40a5b85f18b69c89c638 upstream.
"a * (1 << b)" == "a << b".
No change in generated code.
Signed-off-by: Geert
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By
Biju Das
·
#9009
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[PATCH 5.10.y-cip 11/24] clk: renesas: rzg2l: Remove unused notifiers
From: Phil Edworthy <phil.edworthy@...>
commit 53367bd28f3bf143355e66f20cb6cb83b70e9122 upstream.
notifiers is not used.
Signed-off-by: Phil Edworthy <phil.edworthy@...>
Link:
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From: Phil Edworthy <phil.edworthy@...>
commit 53367bd28f3bf143355e66f20cb6cb83b70e9122 upstream.
notifiers is not used.
Signed-off-by: Phil Edworthy <phil.edworthy@...>
Link:
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By
Biju Das
·
#9008
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[PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream.
The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers
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commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream.
The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers
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By
Biju Das
·
#9007
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[PATCH 5.10.y-cip 09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC
commit 678eb67513a963e5ce00a4ed6a07a5722bd1267e upstream.
Document the device tree binding for the Renesas RZ/V2L SoC.
Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad
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commit 678eb67513a963e5ce00a4ed6a07a5722bd1267e upstream.
Document the device tree binding for the Renesas RZ/V2L SoC.
Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad
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By
Biju Das
·
#9006
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[PATCH 5.10.y-cip 08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
commit 4decd2e54b61686787f36b727d2772e067a46ea5 upstream.
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and
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commit 4decd2e54b61686787f36b727d2772e067a46ea5 upstream.
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and
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By
Biju Das
·
#9005
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[PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit b289cdecc7c3e25e001cde260c882e4d9a8b0772 upstream.
As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be
1600 MHz,
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit b289cdecc7c3e25e001cde260c882e4d9a8b0772 upstream.
As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be
1600 MHz,
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By
Biju Das
·
#9004
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[PATCH 5.10.y-cip 06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries
commit f0b62b0bbedcdfde18116080605cebd9beec4ee9 upstream.
Add GPU clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar
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commit f0b62b0bbedcdfde18116080605cebd9beec4ee9 upstream.
Add GPU clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar
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By
Biju Das
·
#9003
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[PATCH 5.10.y-cip 05/24] clk: renesas: r9a07g044: Add mux and divider for G clock
commit 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 upstream.
G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.
This patch adds a mux and divider for getting
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commit 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 upstream.
G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.
This patch adds a mux and divider for getting
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By
Biju Das
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#9002
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[PATCH 5.10.y-cip 04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
commit 81a27b1f69022174567e8237d3de2534821671ba upstream.
Enable the microSD card slot connected to SDHI1 on the RZ/G2LC SMARC
platform by removing the sdhi1 override which disabled it, and by
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commit 81a27b1f69022174567e8237d3de2534821671ba upstream.
Enable the microSD card slot connected to SDHI1 on the RZ/G2LC SMARC
platform by removing the sdhi1 override which disabled it, and by
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By
Biju Das
·
#9001
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[PATCH 5.10.y-cip 03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
commit 7ca0ce6478c6803c9f86e7366f5634de9c096207 upstream.
RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0.
Both these interfaces are mutually exclusive and the SD0 device
selection is
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commit 7ca0ce6478c6803c9f86e7366f5634de9c096207 upstream.
RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0.
Both these interfaces are mutually exclusive and the SD0 device
selection is
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By
Biju Das
·
#9000
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[PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
commit ce0c63b6a5ef86208d1008ce6c42a7a7180aaf75 upstream.
Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock
It
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commit ce0c63b6a5ef86208d1008ce6c42a7a7180aaf75 upstream.
Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock
It
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By
Biju Das
·
#8999
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[PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
commit 3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd upstream.
The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID.
RZ/G2LC has fewer peripherals compared to RZ/G2L.
SSI (3 channels vs
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commit 3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd upstream.
The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID.
RZ/G2LC has fewer peripherals compared to RZ/G2L.
SSI (3 channels vs
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By
Biju Das
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#8998
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