From: Jan Kiszka <jan.kiszka@...> This reverts commit 32ab6f27ac8264da14ff3b8dc17da1013fb5560f. Misplaced in 4.4 because there is no btn_check_timer in this kernel. Signed-off-by: Jan

cip-gitlab/ci/pavel/linux-test baseline-nfs: 14 runs, 3 regressions (v5.10.131-cip13) Regressions Summary ------------------- platform | arch | lab | compiler | defconfig

cip-gitlab/ci/pavel/linux-test baseline: 36 runs, 6 regressions (v5.10.131-cip13) Regressions Summary ------------------- platform | arch | lab | compiler | defconfig

Hi Pavel, we have a build-regression in 4.4.302-cip70: ../sound/soc/codecs/rt5645.c: In function 'rt5645_i2c_remove': ../sound/soc/codecs/rt5645.c:3683:24: error: 'struct rt5645_priv' has no

cip-gitlab/ci/pavel/linux-test build: 127 builds: 3 failed, 124 passed, 4 errors, 9 warnings (v5.10.131-cip13) Full Build Summary:

Hi! Series looks okay to me. I can apply it if there are no other commands (and if it passes testing). Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director:

Hi! Ok, so this reuse is quite interesting. They share the same source file, but the file will be different basen on config options. If you enable CONFIG_CLK_R9A07G044, you get g044 support but

Hi! Git is a bit unhappy with blank lines -- Applying: arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK .git/rebase-apply/patch:171: new blank line at

This breaks something when building kas-cip.yml:kas/board/qemu-arm64.yml:kas/opt/5.10.yml:kas/opt/bullseye.yml:kas/opt/ebg-secure-boot-snakeoil.yml: NOTE: Executing Tasks ERROR: cip-core-image-1.0-r0

commit fa00d6dc19283bee13f0390546f741293f6d2d9a upstream. SCIF1 interface is available on PMOD1 connector (CN7) on carrier board. This patch adds pinmux and scif1 node to carrier board dtsi file

commit 2ed3b5d9540b246d7a1ec98971914ee810b40086 upstream. RZ/G2LC SoM uses DIP-SWitch SW1 for various pin multiplexing functions. This patch describes DIP-SWitch SW1 settings on SoM and adds

commit 726fd781195dc99cdcb60b2678694bfa5ccd1825 upstream. RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is different. Different pin mapping is possible on SoM. For eg:- RZ/G2L

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> commit ca9df4a75a208f3294a9a09b84ffa1bc89d3e0df upstream. Enable support for the Renesas RZ/V2L SoC. Signed-off-by: Lad Prabhakar

commit f91c4c74796acca0a5a3bde747948a844eb2c30b upstream. Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2): - memory - External input clock - CPG - Pin controller - SCIF -

commit 7c2b8198f4f321df03e285a931fab2a33668c88d upstream. The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only difference being that the RZ/V2L SoC has additional DRP-AI IP

commit 654f89f9496db716c4e9a79c3c6193d57cfaa963 upstream. Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet Interface is identical to one found on the RZ/G2L SoC. No driver

commit 2e08ab0427fe3e33a92a37cfe3b6db340ab7397f upstream. Update rzg2l_gpio_register() to use driver data for chip->names and check for gpio-range. This allows reusing the driver for SoC's with

commit 0c8fce49f24e7c8ee2bdff4761f414ad59bfa29a upstream. RZ/V2L uses the RZ/G2L GPIO and pinctrl driver. Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled. Update the description for RZ/V2L pin

commit c07b19de2f7ac91662aa99767815a258da6ef16f upstream. Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package- and pin-compatible with RZ/G2L. No driver changes are required as

commit a359101c7c6404d917a19d52133305ea284a0197 upstream. Add SCI binding documentation for Renesas RZ/V2L SoC. No driver changes are required as generic compatible string "renesas,sci" will be used