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[PATCH 5.10.y-cip 17/29] arm64: dts: renesas: r9a07g044: Add OSTM nodes
From: Biju Das <biju.das.jz@...>
commit 59a7d68b69846ac012c33c1ac425b9388661d1f2 upstream.
Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das
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From: Biju Das <biju.das.jz@...>
commit 59a7d68b69846ac012c33c1ac425b9388661d1f2 upstream.
Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das
|
By
Lad Prabhakar
·
#7980
·
|
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[PATCH 5.10.y-cip 16/29] clocksource/drivers/renesas,ostm: Make RENESAS_OSTM symbol visible
From: Biju Das <biju.das.jz@...>
commit a2807f657976b943bf0eb81d026398d28aa89863 upstream.
As RZ/G2L uses the ARM Architected Timer as system timer, enabling
the OSTM is not
|
From: Biju Das <biju.das.jz@...>
commit a2807f657976b943bf0eb81d026398d28aa89863 upstream.
As RZ/G2L uses the ARM Architected Timer as system timer, enabling
the OSTM is not
|
By
Lad Prabhakar
·
#7979
·
|
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[PATCH 5.10.y-cip 15/29] clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM support
From: Biju Das <biju.das.jz@...>
commit 3a3e9f23c2cae907677a236fa547610ca747e6fb upstream.
RZ/G2L SoC has Generic Timer Module(a.k.a OSTM) which needs to
deassert the reset line before
|
From: Biju Das <biju.das.jz@...>
commit 3a3e9f23c2cae907677a236fa547610ca747e6fb upstream.
RZ/G2L SoC has Generic Timer Module(a.k.a OSTM) which needs to
deassert the reset line before
|
By
Lad Prabhakar
·
#7978
·
|
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[PATCH 5.10.y-cip 14/29] reset: Add of_reset_control_get_optional_exclusive()
From: Biju Das <biju.das.jz@...>
commit c4f5b30dda01f2f6979a9681142de454991182ee upstream.
Add optional variant of of_reset_control_get_exclusive(). If the
requested reset is not
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From: Biju Das <biju.das.jz@...>
commit c4f5b30dda01f2f6979a9681142de454991182ee upstream.
Add optional variant of of_reset_control_get_exclusive(). If the
requested reset is not
|
By
Lad Prabhakar
·
#7977
·
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[PATCH 5.10.y-cip 13/29] dt-bindings: timer: renesas: ostm: Document Renesas RZ/G2L OSTM
From: Biju Das <biju.das.jz@...>
commit 92d06a3f67ad809649d26aa7698e4d42362585a8 upstream.
Document the General Timer Module(a.k.a OSTM) found on the RZ/G2L SoC.
Signed-off-by: Biju Das
|
From: Biju Das <biju.das.jz@...>
commit 92d06a3f67ad809649d26aa7698e4d42362585a8 upstream.
Document the General Timer Module(a.k.a OSTM) found on the RZ/G2L SoC.
Signed-off-by: Biju Das
|
By
Lad Prabhakar
·
#7976
·
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[PATCH 5.10.y-cip 12/29] clk: renesas: r9a07g044: Add OSTM clock and reset entries
From: Biju Das <biju.das.jz@...>
commit 161450134ae9bab3778c5f5732941162626d0eaa upstream.
Add OSTM{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das
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From: Biju Das <biju.das.jz@...>
commit 161450134ae9bab3778c5f5732941162626d0eaa upstream.
Add OSTM{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das
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By
Lad Prabhakar
·
#7975
·
|
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[PATCH 5.10.y-cip 11/29] watchdog: Add Watchdog Timer driver for RZ/G2L
From: Biju Das <biju.das.jz@...>
commit 2cbc5cd0b55fa2310cc557c77b0665f5e00272de upstream.
Add Watchdog Timer driver for RZ/G2L SoC.
WDT IP block supports normal watchdog timer function
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From: Biju Das <biju.das.jz@...>
commit 2cbc5cd0b55fa2310cc557c77b0665f5e00272de upstream.
Add Watchdog Timer driver for RZ/G2L SoC.
WDT IP block supports normal watchdog timer function
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By
Lad Prabhakar
·
#7974
·
|
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[PATCH 5.10.y-cip 10/29] units: Add SI metric prefix definitions
From: Andy Shevchenko <andriy.shevchenko@...>
commit 26471d4a6cf8d5d0bd0fb55c7169de7d67cc703a upstream.
Sometimes it's useful to have well-defined SI metric prefix to be used
to
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From: Andy Shevchenko <andriy.shevchenko@...>
commit 26471d4a6cf8d5d0bd0fb55c7169de7d67cc703a upstream.
Sometimes it's useful to have well-defined SI metric prefix to be used
to
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By
Lad Prabhakar
·
#7973
·
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[PATCH 5.10.y-cip 09/29] dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L
From: Biju Das <biju.das.jz@...>
commit ab02a00c9e32a5eb1525689b990ad9d345f0832e upstream.
Describe the WDT hardware in the RZ/G2L series.
Signed-off-by: Biju Das
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From: Biju Das <biju.das.jz@...>
commit ab02a00c9e32a5eb1525689b990ad9d345f0832e upstream.
Describe the WDT hardware in the RZ/G2L series.
Signed-off-by: Biju Das
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By
Lad Prabhakar
·
#7972
·
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[PATCH 5.10.y-cip 08/29] clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
From: Biju Das <biju.das.jz@...>
commit dc446cba4301bbe2dbe16711091635d987626410 upstream.
Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and
CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match
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From: Biju Das <biju.das.jz@...>
commit dc446cba4301bbe2dbe16711091635d987626410 upstream.
Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and
CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match
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By
Lad Prabhakar
·
#7971
·
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[PATCH 5.10.y-cip 07/29] clk: renesas: r9a07g044: Add WDT clock and reset entries
From: Biju Das <biju.das.jz@...>
commit 073da9e7c768b0d81f9ce22cc907227450612d88 upstream.
Add WDT{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das
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From: Biju Das <biju.das.jz@...>
commit 073da9e7c768b0d81f9ce22cc907227450612d88 upstream.
Add WDT{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das
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By
Lad Prabhakar
·
#7970
·
|
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[PATCH 5.10.y-cip 06/29] arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board
commit 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 upstream.
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board. This patch adds pinmux and spi1 nodes to the carrier
board
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commit 7dd4fdec402e196f7a5bf519ea1bdb14b358cfa2 upstream.
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board. This patch adds pinmux and spi1 nodes to the carrier
board
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By
Lad Prabhakar
·
#7969
·
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[PATCH 5.10.y-cip 05/29] arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodes
commit a5c29f61466995d0d2c1370c709ef7fda534d386 upstream.
Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by:
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commit a5c29f61466995d0d2c1370c709ef7fda534d386 upstream.
Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by:
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By
Lad Prabhakar
·
#7968
·
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[PATCH 5.10.y-cip 04/29] spi: spi-rspi: Drop redeclaring ret variable in qspi_transfer_in()
commit 1d734f592e1a1d41af80e90001d109cec1c98fb4 upstream.
"ret" variable is already declared in qspi_transfer_in() at the
beginning of function, drop redeclaring ret in the if block,
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commit 1d734f592e1a1d41af80e90001d109cec1c98fb4 upstream.
"ret" variable is already declared in qspi_transfer_in() at the
beginning of function, drop redeclaring ret in the if block,
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By
Lad Prabhakar
·
#7967
·
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[PATCH 5.10.y-cip 03/29] spi: spi-rspi: Add support to deassert/assert reset line
commit aadbff4af5c90919cbe67e2c4d77c68cdefa454e upstream.
On RZ/G2L SoC we need to explicitly deassert the reset line
for the device to work, use this opportunity to deassert/assert
reset line in
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commit aadbff4af5c90919cbe67e2c4d77c68cdefa454e upstream.
On RZ/G2L SoC we need to explicitly deassert the reset line
for the device to work, use this opportunity to deassert/assert
reset line in
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By
Lad Prabhakar
·
#7966
·
|
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[PATCH 5.10.y-cip 02/29] spi: dt-bindings: renesas,rspi: Document RZ/G2L SoC
commit 5a8f8542e34b6469cd5c5a3d075fa5977d90775e upstream.
Add RSPI binding documentation for Renesas RZ/G2L SoC.
RSPI block is identical to one found on RZ/A, so no driver changes are
required. The
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commit 5a8f8542e34b6469cd5c5a3d075fa5977d90775e upstream.
Add RSPI binding documentation for Renesas RZ/G2L SoC.
RSPI block is identical to one found on RZ/A, so no driver changes are
required. The
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By
Lad Prabhakar
·
#7965
·
|
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[PATCH 5.10.y-cip 01/29] clk: renesas: r9a07g044: Add RSPI clock and reset entries
commit e7d960cd6afd56d8c6d4408b6b8a59c91baafcc2 upstream.
Add RSPI{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by:
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commit e7d960cd6afd56d8c6d4408b6b8a59c91baafcc2 upstream.
Add RSPI{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by:
|
By
Lad Prabhakar
·
#7964
·
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[PATCH 5.10.y-cip 00/29] Add RSPI/OSTM/WDT/TSU/OPP support to Renesas RZ/G2L SoC
Hi All,
This patch series adds support for following to Renesas RZ/RGL SoC:
* RSPI
* WDT
* OSTM
* TSU/OPP/IPA
All the patches have been cherry-picked from v5.17 release.
Cheers,
Prabhakar
Andy
|
Hi All,
This patch series adds support for following to Renesas RZ/RGL SoC:
* RSPI
* WDT
* OSTM
* TSU/OPP/IPA
All the patches have been cherry-picked from v5.17 release.
Cheers,
Prabhakar
Andy
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By
Lad Prabhakar
·
#7963
·
|
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cip-gitlab/ci/pavel/linux-test smc: 7 runs, 1 regressions (v4.4-st5-1479-ga84d0db6dfc6)
#kernelci
cip-gitlab/ci/pavel/linux-test smc: 7 runs, 1 regressions (v4.4-st5-1479-ga84d0db6dfc6)
Regressions Summary
-------------------
platform | arch | lab | compiler |
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cip-gitlab/ci/pavel/linux-test smc: 7 runs, 1 regressions (v4.4-st5-1479-ga84d0db6dfc6)
Regressions Summary
-------------------
platform | arch | lab | compiler |
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By
kernelci.org bot <bot@...>
·
#7962
·
|
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cip-gitlab/ci/pavel/linux-test ltp-timers: 6 runs, 4 regressions (v4.4-st5-1479-ga84d0db6dfc6)
#kernelci
cip-gitlab/ci/pavel/linux-test ltp-timers: 6 runs, 4 regressions (v4.4-st5-1479-ga84d0db6dfc6)
Regressions Summary
-------------------
platform | arch | lab | compiler |
|
cip-gitlab/ci/pavel/linux-test ltp-timers: 6 runs, 4 regressions (v4.4-st5-1479-ga84d0db6dfc6)
Regressions Summary
-------------------
platform | arch | lab | compiler |
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By
kernelci.org bot <bot@...>
·
#7961
·
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