From: Biju Das <biju.das.jz@...> commit e93c1373613fb2f3e59db5f13271f155820e6a67 upstream. As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV and CPG_PL2_DDIV(for P0) shares

commit 17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5 upstream. Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh

commit ef3c613ccd68a78727b817c3dacf4a68d1ffc67f upstream. Add CPG core wrapper for RZ/G2L family. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@...>. Signed-off-by: Lad

From: Biju Das <biju.das.jz@...> commit 3b2cd60689fa439481f535ee4463fb223a276f43 upstream. Add serial support for RZ/G2L SoC with earlycon and extended mode register

commit 403921373799a133e41b59cb730e2c4239663f51 upstream. Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 8.3 ("Clock List") of the RZ/G2L

commit f8ec89126a72b399e63399d8d21fd413f4059f00 upstream. Document the device tree bindings of the Renesas RZ/G2L SoC clock driver in

commit 92e06e12212abe4b27ff18445a0f88e6b5236331 upstream. Document R9A07G044 SoC variants, common compatiable string "renesas,scif-r9a07g044" is added for RZ/G2L and RZ/G2LC SoC. Signed-off-by: Lad

Hi All, This patch series adds the following: * Serial support * Clock support * Initial RZ/G2L SoC DTSI - CPU - CPG - GIC * Initial device tree for RZ/G2L SMARC EVK - memory - External

cip/linux-5.10.y-cip baseline: 137 runs, 1 regressions (v5.10.83-cip1-7-geb3270fae08d) Regressions Summary ------------------- platform | arch | lab | compiler |

cip/linux-5.10.y-cip build: 175 builds: 3 failed, 172 passed, 4 errors, 10 warnings (v5.10.83-cip1-7-geb3270fae08d) Full Build Summary:

Hello, We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure. If the board is not accepted as a CIP reference board, we would still

Hi Jan, I may not be able to attend today for personal reason. So, I'll email my work this week. * I released v4.19.220-cip63 and v4.4.294-cip66 * I reviewed 5.10.85. * I reviewed patches for

Hi! Looks good to me too. I have series ready due to testing, so I'll push it. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235

Hi! This one is actually quite interesting. Untrusted users should not normally have shell access on embedded systems, but it highlights topic of coredumps. Default config of coredumping is

Hi all, Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today. Our channel is the following: irc:irc.libera.chat:6667/cip The IRC meeting

Hi ! <nobuhiro1.iwamatsu@...> wrote: Thank you. LGTM ! Regards, -- Masami Ichikawa Cybertrust Japan Co., Ltd. Email :masami.ichikawa@...

Hi, I created a patch which revise this issue. I attached this mail. Best regards, Nobuhiro ________________________________________ 差出人: cip-dev@...

Hi! LGTM. I can merge this seriese, If there is no objection. Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...> Best regards,

Hi all, I think I need to add the board to LAB first. Of course, source code reviews and build tests are possible. And If my understand is correctoly, I think this is a new board that is not on

Hi ! It's this week's CVE report. This week reported ten new CVEs and two of them aren't fixed in the mainline yet. * New CVEs CVE-2021-0961: In quota_proc_write of xt_quota2.c, there is a