From: Geert Uytterhoeven <geert+renesas@...> commit 29db30c45f07c929c86c40a5b85f18b69c89c638 upstream. "a * (1 << b)" == "a << b". No change in generated code. Signed-off-by: Geert

From: Phil Edworthy <phil.edworthy@...> commit 53367bd28f3bf143355e66f20cb6cb83b70e9122 upstream. notifiers is not used. Signed-off-by: Phil Edworthy <phil.edworthy@...> Link:

commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream. The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers

commit 678eb67513a963e5ce00a4ed6a07a5722bd1267e upstream. Document the device tree binding for the Renesas RZ/V2L SoC. Signed-off-by: Biju Das <biju.das.jz@...> Signed-off-by: Lad

commit 4decd2e54b61686787f36b727d2772e067a46ea5 upstream. Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> commit b289cdecc7c3e25e001cde260c882e4d9a8b0772 upstream. As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600 MHz,

commit f0b62b0bbedcdfde18116080605cebd9beec4ee9 upstream. Add GPU clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar

commit 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 upstream. G clock is sourced from PLL3 and PLL6. The output of the mux is connected to divider. This patch adds a mux and divider for getting

commit 81a27b1f69022174567e8237d3de2534821671ba upstream. Enable the microSD card slot connected to SDHI1 on the RZ/G2LC SMARC platform by removing the sdhi1 override which disabled it, and by

commit 7ca0ce6478c6803c9f86e7366f5634de9c096207 upstream. RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is

commit ce0c63b6a5ef86208d1008ce6c42a7a7180aaf75 upstream. Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2): - memory - External input clock - SCIF - GbEthernet - Audio Clock It

commit 3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd upstream. The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID. RZ/G2LC has fewer peripherals compared to RZ/G2L. SSI (3 channels vs

This patch series aims to add Basic board support for SMARC EVK based on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same SMARC EVK board, but SoM is different and pin mapping of SoM module

Thanks, applied. Jan -- Siemens AG, Technology Competence Center Embedded Linux

Thanks, applied. Jan -- Siemens AG, Technology Competence Center Embedded Linux

[ANNOUNCE] Release v4.4.302-cip70 Hi all, CIP kernel team has released Linux kernel v4.4.302-cip70. This applies the required fixes for 4.4.y up to 4.9.320 of the 4.9.y tree. You can get this

From: Quirin Gylstorff <quirin.gylstorff@...> Remove the kas option for efibootguard as it cannot build a image. Move the package installation for swupdate to the include. Quirin Gylstorff

From: Quirin Gylstorff <quirin.gylstorff@...> A build with only the option `kas/efibootguard.yml` will not succeed. Move the content to a include in the image directory and the adapt the

From: Quirin Gylstorff <quirin.gylstorff@...> Signed-off-by: Quirin Gylstorff <quirin.gylstorff@...> --- kas/opt/swupdate.yml | 4 ---- recipes-core/images/swupdate.inc |

Hi all, Just a heads-up that lab-cip-renesas is currently offline due to some networking issues. Hopefully it'll be back up again today, IT gods willing. Apologies for the inconvenience. Kind