commit 61a6d854b9555b420fbfae62ef26baa8b9493b32 upstream. rpcif_enable_rpm calls pm_runtime_enable, so rpcif_disable_rpm needs to call pm_runtime_disable and not pm_runtime_put_sync. Fixes:

commit a0453f4ed066cae651b3119ed11f52d31dae1eca upstream. In the error path of rpcif_manual_xfer() the value of ret is overwritten by value returned by reset_control_reset() function and thus

From: Sergei Shtylyov <sergei.shtylyov@...> commit ca7d8b980b67f133317525c4273e144116ee1ae5 upstream. Add the memory driver for Renesas RPC-IF which registers either SPI or HyperFLash

From: Sergei Shtylyov <sergei.shtylyov@...> commit ab1c362061d92556bd96fd2c0b188f8e4223e3e3 upstream. Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI flash or HyperFlash

Hi Nobuhiro, Pavel, This patch series adds SPI driver for the Renesas RPC-IF. Alongside relevant changes for spi-mem have been also backported. This enables accessing SPI flash chip connected to

cip/linux-4.19.y-cip baseline: 239 runs, 6 regressions (v4.19.163-cip40-5-g95fea62f9f453) Regressions Summary ------------------- platform | arch | lab | compiler |

cip/linux-4.19.y-cip build: 130 builds: 0 failed, 130 passed, 48 warnings (v4.19.163-cip40-5-g95fea62f9f453) Full Build Summary:

Hi! I applied your recent patches, and pushed the result out: 95fea62f9f4534c3b963acd44f03754d9fe0829a dt-bindings: thermal: rcar-gen3-thermal: Add r8a774e1

Hi, When I try to submit a MR on https://gitlab.com/cip-project/cip-kernel/cip-kernel-sec, I get: 500 Whoops, something went wrong on our end. Try refreshing the page, or going back and

Hi! This and dt-bindings: PCI: rcar: Add missing RZ/G2 SoC's series looks okay to me. I can apply it if there are no other comments. Best regards, Pavel -- DENX Software Engineering GmbH,

Hi! Looks good to me. I can apply it to 4.19-cip if there are no other comments. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235

Hi! Looks good to me. I can apply it to 4.19-cip if there are no other comments. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235

Hi! Starting some testing would be good; defconfigs would work. We'll need to notify cip-members, but I assume actual replies from members will need some time. They should be, thanks to our

Hello, [...] I can use some generic defconfigs to start if you like. But yes, ideally we need CIP configs added to cip-kernel-config. Perhaps an email needs to go to cip-members for this? That's

commit adfe9285bed09264bf99689c4a6e932f0134cdb1 upstream. Document RZ/G2H (R8A774E1) SoC bindings. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Geert

commit 64fc0a030987eec45c5362618bacdef7227783d5 upstream. Document the RZ/G2H (a.k.a. R8A774E1) SoC in the R-Car PCIe bingings. [shimoda: minor change the subject and description] Link:

From: Fabrizio Castro <fabrizio.castro@...> commit 2ca98a46435c45f6b749b6ed4d9177f230e3cd12 upstream. Add PCIe support for the RZ/G2N (a.k.a. R8A774B1). Signed-off-by: Fabrizio Castro

Hi All, Both the patches have been cherry picked from v5.11-rc2. Note the DT nodes for r8a774b1 and r8a774e1 have been already added into CIP it was just the documentation which was missed

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...> commit db08e6c0e2513d1341369ec6a4f1774ee20b290b upstream. Document RZ/G2H (R8A774E1) SoC in the Renesas TMU

From: Geert Uytterhoeven <geert+renesas@...> commit f3c6c120614cfb02827ee7bbe6c4240847cc5f12 upstream. The R-Car PCIe controller does not use interrupts when configured for endpoint mode,