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[PATCH 5.10.y-cip 08/24] iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit 024b58a30274a9e28d5c7c17b1ec405714047f2a upstream.
ADC block is common on Renesas RZ/G2L and RZ/V2L SoC's, so instead of
adding
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit 024b58a30274a9e28d5c7c17b1ec405714047f2a upstream.
ADC block is common on Renesas RZ/G2L and RZ/V2L SoC's, so instead of
adding
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By
Biju Das
·
#8794
·
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[PATCH 5.10.y-cip 07/24] ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L
commit cc691ba94cf8d6c586076ed489bb9d385a2650ad upstream.
The SSI block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so
instead of adding dependency for each SoC's add dependency on
commit cc691ba94cf8d6c586076ed489bb9d385a2650ad upstream.
The SSI block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so
instead of adding dependency for each SoC's add dependency on
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By
Biju Das
·
#8793
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[PATCH 5.10.y-cip 06/24] soc: renesas: Kconfig: Introduce ARCH_RZG2L config option
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit 088659ad2a830124407edc38da278010c95bcc96 upstream.
The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP
blocks
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit 088659ad2a830124407edc38da278010c95bcc96 upstream.
The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP
blocks
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By
Biju Das
·
#8792
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[PATCH 5.10.y-cip 05/24] soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit b89acaf8cad188d9a1387d3049ae036a10d9a1f3 upstream.
Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044
and
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
commit b89acaf8cad188d9a1387d3049ae036a10d9a1f3 upstream.
Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044
and
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By
Biju Das
·
#8791
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[PATCH 5.10.y-cip 04/24] soc: renesas: Add support for reading product revision for RZ/G2L family
commit cb5508e47e60b85ac033edd8c52245ad51360eb4 upstream.
As per RZ/G2L HW manual (Rev.1.00 Sep, 2021) DEV_ID [31:28] indicates
product revision. Use this information to populate the revision
commit cb5508e47e60b85ac033edd8c52245ad51360eb4 upstream.
As per RZ/G2L HW manual (Rev.1.00 Sep, 2021) DEV_ID [31:28] indicates
product revision. Use this information to populate the revision
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By
Biju Das
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#8790
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[PATCH 5.10.y-cip 03/24] soc: renesas: Identify RZ/V2L SoC
commit 860122d80251c64484883324128ca82fa35423ef upstream.
Add support for identifying the RZ/V2L (R9A07G054) SoC.
Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar
commit 860122d80251c64484883324128ca82fa35423ef upstream.
Add support for identifying the RZ/V2L (R9A07G054) SoC.
Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar
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By
Biju Das
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#8789
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[PATCH 5.10.y-cip 02/24] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
commit 4b4a0fd666303a06bbe159552bc055b490b77cdc upstream.
Add DT binding documentation for the SYSC controller found on the RZ/V2L
SoC. This SYSC controller is almost identical to the one found on
commit 4b4a0fd666303a06bbe159552bc055b490b77cdc upstream.
Add DT binding documentation for the SYSC controller found on the RZ/V2L
SoC. This SYSC controller is almost identical to the one found on
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By
Biju Das
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#8788
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[PATCH 5.10.y-cip 01/24] soc: renesas: Consolidate product register handling
From: Geert Uytterhoeven <geert+renesas@...>
commit 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 upstream.
Currently renesas_soc_init() scans the whole device tree up to three
times, to find a
From: Geert Uytterhoeven <geert+renesas@...>
commit 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 upstream.
Currently renesas_soc_init() scans the whole device tree up to three
times, to find a
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By
Biju Das
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#8787
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[PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline
This patch series are backported from Mainline for supporting
future SoCs as well as various bugs and improvements related to
RZ/g2L SMARC EVK Platform.
All these patches are cherry-picked from
This patch series are backported from Mainline for supporting
future SoCs as well as various bugs and improvements related to
RZ/g2L SMARC EVK Platform.
All these patches are cherry-picked from
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By
Biju Das
·
#8786
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Re: [isar-cip-core] README.secuirty-testing.md: Add steps to verify CIP security image
At least it made it to my inbox - and got lost there as well. Applied now.
Thanks,
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
At least it made it to my inbox - and got lost there as well. Applied now.
Thanks,
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
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By
Jan Kiszka
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#8785
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Re: cip/linux-4.4.y-cip build: 187 builds: 5 failed, 182 passed, 6 errors, 200 warnings (v4.4.302-cip69-508-gd887d54a1be6)
#kernelci
Hi all,
project.org wrote:
The log tells me:
arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3
arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’
AFAIK armv3 support
Hi all,
project.org wrote:
The log tells me:
arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3
arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’
AFAIK armv3 support
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By
Florian Bezdeka
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#8784
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[PATCH [5.10.y-cip] 13/13] watchdog: rzg2l_wdt: Add set_timeout callback
commit 4055ee81009e606e830af1acd9e2e35a36249713 upstream.
This patch adds support for set_timeout callback.
Once WDT is started, the WDT cycle setting register(WDTSET) can be updated
only after
commit 4055ee81009e606e830af1acd9e2e35a36249713 upstream.
This patch adds support for set_timeout callback.
Once WDT is started, the WDT cycle setting register(WDTSET) can be updated
only after
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By
Biju Das
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#8783
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[PATCH [5.10.y-cip] 12/13] watchdog: rzg2l_wdt: Use force reset for WDT reset
commit f43e6ddbd7d7b63b9e71927a1f50860f8d55f9cc upstream.
This patch uses the force reset(WDTRSTB) for triggering WDT reset for
restart callback. This method(ie, Generate Reset (WDTRSTB) Signal
commit f43e6ddbd7d7b63b9e71927a1f50860f8d55f9cc upstream.
This patch uses the force reset(WDTRSTB) for triggering WDT reset for
restart callback. This method(ie, Generate Reset (WDTRSTB) Signal
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By
Biju Das
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#8782
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[PATCH [5.10.y-cip] 11/13] watchdog: rzg2l_wdt: Add error check for reset_control_deassert
commit baf1aace9ad15401f08e048a7f1fdec79821bc61 upstream.
If reset_control_deassert() fails, then we won't be able to
access the device registers. Therefore check the return code
commit baf1aace9ad15401f08e048a7f1fdec79821bc61 upstream.
If reset_control_deassert() fails, then we won't be able to
access the device registers. Therefore check the return code
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By
Biju Das
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#8781
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[PATCH [5.10.y-cip] 10/13] watchdog: rzg2l_wdt: Fix reset control imbalance
commit 33d04d0fdba9fae18c7d58364643d2c606a43dba upstream.
Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls reset_control_
deassert() which results in a reset control imbalance.
This patch fixes
commit 33d04d0fdba9fae18c7d58364643d2c606a43dba upstream.
Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls reset_control_
deassert() which results in a reset control imbalance.
This patch fixes
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By
Biju Das
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#8780
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[PATCH [5.10.y-cip] 09/13] watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'
commit e4cf89596c1f1e33309556699f910ced4abbaf44 upstream.
This patch fixes the issue 'BUG: Invalid wait context' during restart()
callback by using clk_prepare_enable() instead of
commit e4cf89596c1f1e33309556699f910ced4abbaf44 upstream.
This patch fixes the issue 'BUG: Invalid wait context' during restart()
callback by using clk_prepare_enable() instead of
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By
Biju Das
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#8779
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[PATCH [5.10.y-cip] 08/13] watchdog: rzg2l_wdt: Fix Runtime PM usage
commit 95abafe76297fa057de6c3486ef844bd446bdf18 upstream.
Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls pm_runtime_get() which
results in a usage counter imbalance. This patch fixes this issue
commit 95abafe76297fa057de6c3486ef844bd446bdf18 upstream.
Both rzg2l_wdt_probe() and rzg2l_wdt_start() calls pm_runtime_get() which
results in a usage counter imbalance. This patch fixes this issue
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By
Biju Das
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#8778
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[PATCH [5.10.y-cip] 07/13] watchdog: rzg2l_wdt: Fix 32bit overflow issue
commit ea2949df22a533cdf75e4583c00b1ce94cd5a83b upstream.
The value of timer_cycle_us can be 0 due to 32bit overflow.
For eg:- If we assign the counter value "0xfff" for computing
maxval.
This patch
commit ea2949df22a533cdf75e4583c00b1ce94cd5a83b upstream.
The value of timer_cycle_us can be 0 due to 32bit overflow.
For eg:- If we assign the counter value "0xfff" for computing
maxval.
This patch
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By
Biju Das
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#8777
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[PATCH [5.10.y-cip] 06/13] arm64: defconfig: Enable additional support for Renesas platforms
From: Geert Uytterhoeven <geert+renesas@...>
commit 2e8a3335472461927e57d1741ccf1791ff416075 upstream.
Increase build and test coverage by enabling support for more hardware
present on Renesas
From: Geert Uytterhoeven <geert+renesas@...>
commit 2e8a3335472461927e57d1741ccf1791ff416075 upstream.
Increase build and test coverage by enabling support for more hardware
present on Renesas
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By
Biju Das
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#8776
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[PATCH [5.10.y-cip] 05/13] thermal/drivers/rz2gl: Fix OTP Calibration Register values
commit 2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6 upstream.
As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM)
commit 2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6 upstream.
As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM)
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By
Biju Das
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#8775
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