Hi! #ifdefs here could be reduced... Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194

Hi! This can be refactored to remove if/else nesting. This can be if (desc->nodirmap) return spi_mem_no_dirmap_read(desc, offs, len, buf); if (!(ctlr->mem_ops &&

Hi! If we are doing this kind of cleanups... I'd move "len" declaration inside the if, too... Not that it matters much. Best regards, Pavel Signed-off-by: Pavel Machek (CIP)

Hi! This puts function definition directly into header file; I don't think that will work when multiple files include it. Adding "static inline" is the usual solution for this. Best

Hi! I went through this and "Add missing rpc-if clock on RZ/G2{E,M,N} SoC" series, and they look okay to me. I can apply them if there are no other comments. Best regards, Pavel -- DENX

commit ffcd7f812dec2f1f27fe73b89c17a04ef6586325 upstream. Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das

commit 4356497e9eda8ec7dcd095b1ecd947ffe12917aa upstream. Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das

commit 590567bf6f6d989ba9d0fc406282d7a18cf5fa96 upstream. Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das

commit 89ad953e1e727640e85beb82db3c71d45a59b177 upstream. Add pins, groups and functions for QSPIO[01]. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das

From: Biju Das <biju.das.jz@...> commit 03522a59a9e7e5f464735e907891cd235aa68b1d upstream. This driver supports both RZ/G2E and R-Car E3 SoCs. Optimize pinctrl image size for RZ/G2E, when

From: Biju Das <biju.das.jz@...> commit 74c5fdc5b87a9435d6afbdd7d22c874c160bafc6 upstream. This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N,

From: Biju Das <biju.das.jz@...> commit b8029394efccf48687d9a7fae6c4747b81e35261 upstream. This driver supports both RZ/G2H and R-Car H3 ES2 SoCs. Optimize pinctrl image size for RZ/G2H,

From: Biju Das <biju.das.jz@...> commit 74ce7a8044b07268817828af2d6268801ddc012b upstream. This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M,

Hi All, This patch series optimizes pinctrl driver for size and adds QSPI[01] pins for RZ/G2{H,M,N,E} SoC. All the patches have been cherry picked from v5.11-rc2 Currently the SoC DTSI changes are

commit 40745482eec81bea686cd1b38693191dc7e9ac66 upstream. Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0)

From: Biju Das <biju.das.jz@...> commit fb9805c51793339e0affbc8e3ce2b3210b41c9fa upstream. Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF

From: Biju Das <biju.das.jz@...> commit 13d2617bf224351e78141183ca51971df83a9dd5 upstream. Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF

Hi All, This patch series adds missing rpc-if clock on RZ/G2{E,M,N} SoC's. All the patches have been cherry picked from v5.11-rc2. Cheers, Prabhakar Biju Das (2): clk: renesas: r8a774a1: Add RPC

From: Lukas Wunner <lukas@...> commit 393f981ca5f797b58b882d42b7621fb6e43c7f5b upstream. rpcif_spi_remove() accesses the driver's private data after calling spi_unregister_controller() even

From: Sergei Shtylyov <sergei.shtylyov@...> commit eb8d6d464a27850498dced21a8450e85d4a02009 upstream. Add the SPI driver for the Renesas RPC-IF. It's the "front end" driver using the