From: Biju Das <biju.das@...> commit 5eb08d995564c9f9d4818a84050f7716b73c86cc upstream. Document the RZ/G1N (R8A7744) SoC in the R-Car DU bindings. Signed-off-by: Biju Das

This patch series add DU support for iWave iwg20d platform based on RZ/G1N. This patch series is based on linux-4.4.y-cip and all the patches in this series are cherry-picked from upstream. Biju Das

Hi, yep, that's the reason. The new runners respect the container's entrypoint (i.e. the entrypoint script is begin executed on a CI run). In other words, there shouldn't be any reason to execute

Hello, It doesn't look like there are any recent changes in the .gitlab-ci.yml file. However the GitLab runner we use was upgraded to a newer version since your last build. @Adler, Michael,

Hi! Thanks for the series, applied. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194

Hello, In the latest CI for cip-core/deby/cip-core-buster, I got the following error (and warnings), probably related to kas/docker-entrypoint. $ /kas/docker-entrypoint useradd: user 'builder'

[...] Why still chrony, why not simply systemd timers? Legacy? I'm missing the new dependencies in the top-list. Didn't we agree on listing them flat? This, e.g., pulls python, currently even v2 -

Hi Biju, Pavel, struct soc_device_attribute.data contains an opaque value, just like e.g. of_device_id.data and platform_device_id.driver_data. In some structs, the opaque value is a "void *", in

Hello Kazu and CIP Core working group members, From Renesas, agree with this proposal. Best regards, Kent

Hi,

Hi Pavel, I am adding Dien and Geert to provide feedback on you r questions Regards, Bij

Hi Pavel, Thanks for the feedback.

Hi all, Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today. *Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting

Hi! I have made two comments on the patches, but I believe the series is good enough to merge. I'll do that later if there are no objections. Best regards, Pavel -- DENX Software

Hi! So you are storing bitfield in the pointer, ok. But now you do strange dance with types. I'd understand quirks being unsigned long (because that's same size as void *). I also could understand

Hi! Normally, config option should be close to the end of the series (having it in the begining can be surprising during the bisect, for example). Best regards, Pavel -- DENX Software

commit d8b178741e5ba571fbcc187c9e3cf9c0eaebf328 upstream. Enable the Renesas RZ/G2N (R8A774B1) SoC in the ARM64 defconfig. Signed-off-by: Biju Das <biju.das@...> Link:

commit 83f7f812a8706aa9c23b02d945f670cdef116e2c upstream. Basic support for the HiHope RZ/G2N main board: - Memory, - Main crystal, - Serial console Signed-off-by: Biju Das

commit 9b33e3001b67f9dcd52548db2949f5a04d0b4017 upstream. Basic support for the RZ/G2N (R8A774B1) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by:

commit fc5f3782da3c73bbbe2293551219b2ded0660357 upstream. RZ/G2N (R8A774B1) SoC also has the R-Car Gen3 compatible SCIF and HSCIF ports, so document the SoC specific bindings. Signed-off-by: Biju