From: Geert Uytterhoeven <geert+renesas@...> Improve documentation for the SCIFA/SCIFB Serial Port Control and Data Registers: - State clearly that the RTS and CTS lines are active-low, -

From: Geert Uytterhoeven <geert+renesas@...> Improve documentation for the (H)SCIF Serial Port Register: - Make it clear the RTS and CTS lines are active-low, - Document the bits related to

From: Geert Uytterhoeven <geert+renesas@...> Replace open-coded variants of sci_getreg() by function calls, and drop intermediate variables where appropriate. Signed-off-by: Geert Uytterhoeven

From: Geert Uytterhoeven <geert+renesas@...> Enhance the Renesas SCI UART driver to add support for GPIO-controlled modem lines (CTS, DSR, DCD, RNG, RTS, DTR), using the

From: Geert Uytterhoeven <geert+renesas@...> Documentation/serial/driver clearly states: If the port does not support CTS, DCD or DSR, the driver should indicate that the signal is

From: Geert Uytterhoeven <geert+renesas@...> Some Renesas SCIF UARTs have dedicated lines for RTS/CTS hardware flow control. Whether these lines exist depends on SoC and UART instance inside

From: Geert Uytterhoeven <geert+renesas@...> Amend the DT bindings for the Renesas SCI driver to allow describing optional GPIO-controlled modem lines, which can be used where dedicated modem

This series aims at adding UART support to r8a7743 by backporting the relevant patches from upstream. As per upstream, since two of the serial interfaces live on the camera daughter board, we rework

The priority starts to rise here because new system are coming out that need to start system testing and other processes on a CIP kernel with Spectre mitigations (x86 so far). Can you estimate the

From: Biju Das <biju.das@...> Define the iWave RainboW-G20D-Qseven board dependent part of the SDHI1 device node. Signed-off-by: Biju Das <biju.das@...> Acked-by: Wolfram Sang

From: Biju Das <biju.das@...> Enable the SDHI0 controller on iWave RZG1M Qseven SOM. Signed-off-by: Biju Das <biju.das@...> Acked-by: Wolfram Sang

From: Biju Das <biju.das@...> Add the SDHI controllers to the r8a7743 device tree. Signed-off-by: Biju Das <biju.das@...> Signed-off-by: Simon Horman

From: Biju Das <biju.das@...> Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by: Biju Das

From: Biju Das <biju.das@...> Add support for r8a7743/5 SoC.Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by: Biju Das

This commit renames R8A7743_CLK_SDHI2 to R8A7743_CLK_SDHI1 and R8A7743_CLK_SDHI3 to R8A7743_CLK_SDHI2. This is to make the SDHI clock names of the r8a7743 more similar to upstream

Dear All, this patch series adds SDHI support to the r8a7743 SoC. The only patch that hasn't been backported in this series is: "ARM: shmobile: r8a7743: Rename SDHI clocks" This work has been based

Maybe we should discuss the numbers at board level. Seems like a an interesting project, but it's a one-man show, and I would be careful with relying on it at that point. Jan

Ah, though this seems only available for the admin of the list.

Daniel, I would need to see if there are any caveats, but in the FAQ here are the instructions to get an archive extract:

Hi Jeff, Is there a way to get an archive extracted from the groups.io platform? Daniel