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[cip-core:deby 2/3] security-configuration: apply security polcies using package bbappend

Venkata Pyla
 

From: venkata pyla <venkata.pyla@toshiba-tsip.com>

add package bbappaned files in the security layer that will apply
the security configurations like
e.g: Set password strength in pam configurations
Set audit failure actions in audit package configurations
etc.

Signed-off-by: venkata pyla <venkata.pyla@toshiba-tsip.com>
---
.../audit/audit_debian.bbappend | 20 ++++++++++
.../base-files/base-files_debian.bbappend | 3 ++
.../openssh/openssh_debian.bbappend | 19 +++++++++
.../recipes-debian/pam/libpam_debian.bbappend | 39 +++++++++++++++++++
4 files changed, 81 insertions(+)
create mode 100644 meta-cip-security/recipes-debian/audit/audit_debian.bbappend
create mode 100644 meta-cip-security/recipes-debian/base-files/base-files_debian.bbappend
create mode 100644 meta-cip-security/recipes-debian/openssh/openssh_debian.bbappend
create mode 100644 meta-cip-security/recipes-debian/pam/libpam_debian.bbappend

diff --git a/meta-cip-security/recipes-debian/audit/audit_debian.bbappend b/meta-cip-security/recipes-debian/audit/audit_debian.bbappend
new file mode 100644
index 0000000..c148f27
--- /dev/null
+++ b/meta-cip-security/recipes-debian/audit/audit_debian.bbappend
@@ -0,0 +1,20 @@
+#
+# CIP Security, tiny profile
+#
+# Copyright (c) Toshiba Corporation, 2020
+#
+# SPDX-License-Identifier: MIT
+#
+
+DESCRIPTION = "CIP Security customizations"
+
+pkg_postinst_audit_append() {
+ # CR2.9: Audit storage capacity
+ # CR2.9 RE-1: Warn when audit record storage capacity threshold reached
+ AUDIT_CONF_FILE="$D${sysconfdir}/audit/auditd.conf"
+ sed -i 's/space_left_action = .*/space_left_action = SYSLOG/' $AUDIT_CONF_FILE
+ sed -i 's/admin_space_left_action = .*/admin_space_left_action = SYSLOG/' $AUDIT_CONF_FILE
+
+ # CR2.10: Response to audit processing failures
+ sed -i 's/disk_error_action = .*/disk_error_action = SYSLOG/' $AUDIT_CONF_FILE
+}
diff --git a/meta-cip-security/recipes-debian/base-files/base-files_debian.bbappend b/meta-cip-security/recipes-debian/base-files/base-files_debian.bbappend
new file mode 100644
index 0000000..895dc9f
--- /dev/null
+++ b/meta-cip-security/recipes-debian/base-files/base-files_debian.bbappend
@@ -0,0 +1,3 @@
+do_install_append() {
+ echo "${MACHINE}" > ${D}${sysconfdir}/hostname
+}
diff --git a/meta-cip-security/recipes-debian/openssh/openssh_debian.bbappend b/meta-cip-security/recipes-debian/openssh/openssh_debian.bbappend
new file mode 100644
index 0000000..ddd2bfc
--- /dev/null
+++ b/meta-cip-security/recipes-debian/openssh/openssh_debian.bbappend
@@ -0,0 +1,19 @@
+#
+# CIP Security, tiny profile
+#
+# Copyright (c) Toshiba Corporation, 2020
+#
+# SPDX-License-Identifier: MIT
+#
+
+DESCRIPTION = "CIP Security customizations"
+
+pkg_postinst_${PN}_append() {
+ # CR2.6: Remote session termination
+ # Terminate remote session after inactive time period
+ SSHD_CONFIG="$D${sysconfdir}/ssh/sshd_config"
+ alive_interval=$(sed -n '/ClientAliveInterval/p' "${SSHD_CONFIG}")
+ alive_countmax=$(sed -n '/ClientAliveCountMax/p' "${SSHD_CONFIG}")
+ sed -i "/${alive_interval}/c ClientAliveInterval 120" "${SSHD_CONFIG}"
+ sed -i "/${alive_countmax}/c ClientAliveCountMax 0" "${SSHD_CONFIG}"
+}
diff --git a/meta-cip-security/recipes-debian/pam/libpam_debian.bbappend b/meta-cip-security/recipes-debian/pam/libpam_debian.bbappend
new file mode 100644
index 0000000..c9c1605
--- /dev/null
+++ b/meta-cip-security/recipes-debian/pam/libpam_debian.bbappend
@@ -0,0 +1,39 @@
+#
+# CIP Security, tiny profile
+#
+# Copyright (c) Toshiba Corporation, 2020
+#
+# SPDX-License-Identifier: MIT
+#
+
+DESCRIPTION = "CIP Security customizations"
+
+pkg_postinst_pam-plugin-cracklib_append() {
+ # CR1.7: Strength of password-based authentication
+ # Pam configuration to enforce password strength
+ PAM_PWD_FILE="$D${sysconfdir}/pam.d/common-password"
+ CRACKLIB_CONFIG="password requisite pam_cracklib.so retry=3 minlen=8 maxrepeat=3 ucredit=-1 lcredit=-1 dcredit=-1 ocredit=-1 difok=3 gecoscheck=1 reject_username enforce_for_root"
+ if grep -c "pam_cracklib.so" "${PAM_PWD_FILE}";then
+ sed -i '/pam_cracklib.so/ s/^#*/#/' "${PAM_PWD_FILE}"
+ fi
+ sed -i "0,/^password.*/s/^password.*/${CRACKLIB_CONFIG}\n&/" "${PAM_PWD_FILE}"
+}
+
+pkg_postinst_pam-plugin-tally2_append() {
+ # CR1.11: Unsuccessful login attempts
+ # Lock user account after unsuccessful login attempts
+ PAM_AUTH_FILE="$D${sysconfdir}/pam.d/common-auth"
+ pam_tally="auth required pam_tally2.so deny=3 even_deny_root unlock_time=60 root_unlock_time=60"
+ if grep -c "pam_tally2.so" "${PAM_AUTH_FILE}";then
+ sed -i '/pam_tally2/ s/^#*/#/' "${PAM_AUTH_FILE}"
+ fi
+ sed -i "0,/^auth.*/s/^auth.*/${pam_tally}\n&/" "${PAM_AUTH_FILE}"
+}
+
+
+pkg_postinst_libpam_append() {
+ # CR2.7: Concurrent session control
+ # Limit the concurrent login sessions
+ LIMITS_CONFIG="$D${sysconfdir}/security/limits.conf"
+ echo "* hard maxlogins 2" >> ${LIMITS_CONFIG}
+}
--
2.27.0.windows.1

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[cip-core:deby 1/3] cip-security: Create new layer for cip security

Venkata Pyla
 

From: venkata pyla <venkata.pyla@toshiba-tsip.com>

This layer enables security packages and default configurations
required to evaluate IEC62443-4-2 assessment

Signed-off-by: venkata pyla <venkata.pyla@toshiba-tsip.com>
---
README.md | 5 +++++
kas/opt/security.yml | 32 +++++++++++++++++++++++++++++++
meta-cip-security/conf/layer.conf | 18 +++++++++++++++++
3 files changed, 55 insertions(+)
create mode 100644 kas/opt/security.yml
create mode 100644 meta-cip-security/conf/layer.conf

diff --git a/README.md b/README.md
index f90e040..f59dd0c 100644
--- a/README.md
+++ b/README.md
@@ -88,3 +88,8 @@ LTP test image for QEMU arm64 / hihope-rzg2m

$ ./scripts/kas-build.sh kas/board/qemuarm64.yml:kas/opt/deby.yml:kas/opt/dhcp.yml:kas/opt/ltp.yml

+Create Security image for QEMU x86-64
+-------------------------------------
+
+ $ ./scripts/kas-build.sh kas/board/qemux86-64.yml:kas/opt/deby.yml:kas/opt/security.yml
+
diff --git a/kas/opt/security.yml b/kas/opt/security.yml
new file mode 100644
index 0000000..e84290c
--- /dev/null
+++ b/kas/opt/security.yml
@@ -0,0 +1,32 @@
+#
+# CIP Core tiny profile with Security
+# packages and configuration
+#
+# Copyright (c) 2019 TOSHIBA Corp.
+#
+# SPDX-License-Identifier: MIT
+#
+
+header:
+ version: 8
+
+repos:
+ meta-cip-security:
+ layers:
+ meta-cip-security:
+
+local_conf_header:
+ security: |
+ DISTRO_FEATURES_append += " pam"
+ CORE_IMAGE_EXTRA_INSTALL += " \
+ aide aide-common \
+ openssl openssl-bin \
+ openssh openssh-misc \
+ chrony chronyc \
+ libpam pam-plugin-cracklib pam-plugin-tally2 \
+ syslog-ng \
+ acl \
+ sudo \
+ auditd \
+ util-linux \
+ "
diff --git a/meta-cip-security/conf/layer.conf b/meta-cip-security/conf/layer.conf
new file mode 100644
index 0000000..b015436
--- /dev/null
+++ b/meta-cip-security/conf/layer.conf
@@ -0,0 +1,18 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH =. "${LAYERDIR}:"
+
+# We have recipes-* directories, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
+ ${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "cip-security"
+BBFILE_PATTERN_cip-security = "^${LAYERDIR}/"
+BBFILE_PRIORITY_cip-security = "11"
+
+# This should only be incremented on significant changes that will
+# cause compatibility issues with other layers
+LAYERVERSION_cip-security = "1"
+
+LAYERDEPENDS_cip-security = "debian"
+
+LAYERSERIES_COMPAT_cip-security = "warrior"
--
2.27.0.windows.1

The information contained in this e-mail message and in any
attachments/annexure/appendices is confidential to the
recipient and may contain privileged information.
If you are not the intended recipient, please notify the
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attachments/annexure/appendices. You should not disclose,
copy or otherwise use the information contained in the
message or any annexure. Any views expressed in this e-mail
are those of the individual sender except where the sender
specifically states them to be the views of
Toshiba Software India Pvt. Ltd. (TSIP),Bangalore.

Although this transmission and any attachments are believed to be
free of any virus or other defect that might affect any computer
system into which it is received and opened, it is the responsibility
of the recipient to ensure that it is virus free and no responsibility
is accepted by Toshiba Embedded Software India Pvt. Ltd, for any loss or
damage arising in any way from its use.


[cip-core:deby 0/3] deby security layer changes

Venkata Pyla
 

From: venkata-pyla <venkata.pyla@toshiba-tsip.com>

Added a security layer in deby that will be used for IEC 62443-4-2
certification

venkata pyla (3):
cip-security: Create new layer for cip security
security-configuration: apply security polcies using package bbappend
aide-static: enable aide to build statically

README.md | 5 +++
kas/opt/security.yml | 32 +++++++++++++++
.../conf/include/aide-static-libs.inc | 10 +++++
meta-cip-security/conf/layer.conf | 20 ++++++++++
.../audit/audit_debian.bbappend | 20 ++++++++++
.../base-files/base-files_debian.bbappend | 3 ++
.../openssh/openssh_debian.bbappend | 19 +++++++++
.../recipes-debian/pam/libpam_debian.bbappend | 39 +++++++++++++++++++
8 files changed, 148 insertions(+)
create mode 100644 kas/opt/security.yml
create mode 100644 meta-cip-security/conf/include/aide-static-libs.inc
create mode 100644 meta-cip-security/conf/layer.conf
create mode 100644 meta-cip-security/recipes-debian/audit/audit_debian.bbappend
create mode 100644 meta-cip-security/recipes-debian/base-files/base-files_debian.bbappend
create mode 100644 meta-cip-security/recipes-debian/openssh/openssh_debian.bbappend
create mode 100644 meta-cip-security/recipes-debian/pam/libpam_debian.bbappend

--
2.27.0.windows.1

The information contained in this e-mail message and in any
attachments/annexure/appendices is confidential to the
recipient and may contain privileged information.
If you are not the intended recipient, please notify the
sender and delete the message along with any
attachments/annexure/appendices. You should not disclose,
copy or otherwise use the information contained in the
message or any annexure. Any views expressed in this e-mail
are those of the individual sender except where the sender
specifically states them to be the views of
Toshiba Software India Pvt. Ltd. (TSIP),Bangalore.

Although this transmission and any attachments are believed to be
free of any virus or other defect that might affect any computer
system into which it is received and opened, it is the responsibility
of the recipient to ensure that it is virus free and no responsibility
is accepted by Toshiba Embedded Software India Pvt. Ltd, for any loss or
damage arising in any way from its use.


Re: [cip-kernel-config ][ RFC 1/1] 4.19.y-cip/cip_bbb_defconfig: Add config switches from isar-cip-core

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Quirin Gylstorff
Sent: Friday, August 21, 2020 6:52 PM
To: cip-dev@lists.cip-project.org; sangorrin daniel(サンゴリン ダニエル □SWC◯ACT)
<daniel.sangorrin@toshiba.co.jp>; jan.kiszka@siemens.com
Subject: Re: [cip-dev] [cip-kernel-config ][ RFC 1/1] 4.19.y-cip/cip_bbb_defconfig: Add config switches from
isar-cip-core



On 8/21/20 1:34 AM, Nobuhiro Iwamatsu wrote:
Hi,

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of Quirin Gylstorff
Sent: Monday, August 17, 2020 6:29 PM
To: sangorrin daniel(サンゴリン ダニエル □SWC◯ACT) <daniel.sangorrin@toshiba.co.jp>;
cip-dev@lists.cip-project.org; jan.kiszka@siemens.com
Cc: Quirin Gylstorff <quirin.gylstorff@siemens.com>
Subject: [cip-dev] [cip-kernel-config ][ RFC 1/1] 4.19.y-cip/cip_bbb_defconfig: Add config switches from
isar-cip-core

From: Quirin Gylstorff <quirin.gylstorff@siemens.com>

Add the config switches which exist only in isar-cip-core
to the defconfig in cip-kernel-config for the beagle bone black.
Thanks for your patch.
The cip_bbb_defconfig created by me had minimal functionality enabled. I didn't know that Siemens didn't include
the required features.
So I think this patch is necessary.
However, we think that it is difficult to do it with one defconfig when testing the necessary functions as CIP in
the future.
Therefore, it may be necessary to prepare defconfig for each required function in the future.

By the way, is this only 4.19? Do I need to change RT or 4.4.y?
This patch is only for 4.19. I can prepare a v2 which includes v4.4. As
posted it was intented to show the current difference between the bbb
config in isar-cip-core and cip-kernel-config.
I see.
Would you send a patch for v4.4 as well?

Best regards,
Nobuhiro

Best regards,
Quirin

Best regards,
Nobuhiro

Signed-off-by: Quirin Gylstorff <quirin.gylstorff@siemens.com>
---
4.19.y-cip/arm/cip_bbb_defconfig | 339 +++++++++++++++++++++++++++++++
1 file changed, 339 insertions(+)

diff --git a/4.19.y-cip/arm/cip_bbb_defconfig b/4.19.y-cip/arm/cip_bbb_defconfig
index 3e22365..445cdee 100644
--- a/4.19.y-cip/arm/cip_bbb_defconfig
+++ b/4.19.y-cip/arm/cip_bbb_defconfig
@@ -1,6 +1,9 @@
# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZMA=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
@@ -8,6 +11,7 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
@@ -17,24 +21,67 @@ CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
CONFIG_CGROUP_CPUACCT=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_DEBUG=y
CONFIG_USER_NS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_BPF_SYSCALL=y
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_ARCH_VIRT=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_POWER_AVS_OMAP=y
+CONFIG_POWER_AVS_OMAP_CLASS3=y
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_ARCH_OMAP3=y
+CONFIG_OMAP_MUX_DEBUG=y
CONFIG_SOC_AM33XX=y
CONFIG_ARM_THUMBEE=y
CONFIG_OABI_COMPAT=y
+CONFIG_ARM_ERRATA_411920=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_CMA=y
+CONFIG_SECCOMP=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CMDLINE=""
+CONFIG_KEXEC=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
+# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_BINFMT_MISC=y
CONFIG_PM_DEBUG=y
CONFIG_OPROFILE=y
CONFIG_KPROBES=y
@@ -48,6 +95,8 @@ CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_XFRM_SUB_POLICY=y
CONFIG_NET_KEY=m
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
@@ -74,6 +123,7 @@ CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_TUNNEL=m
+# CONFIG_INET_LRO is not set
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_AMANDA=m
@@ -196,40 +246,108 @@ CONFIG_NET_PKTGEN=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
+CONFIG_PHONET=m
+CONFIG_CAN=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_CFG80211=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_AF_RXRPC=m
+CONFIG_RXKAD=m
+CONFIG_MAC80211=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_OMAP_OCP2SCP=y
+CONFIG_CONNECTOR=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_OOPS=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_OMAP2=y
CONFIG_MTD_UBI=y
CONFIG_OF_OVERLAY=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_NBD=m
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_M25P80=m
+CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_VIRTIO_BLK=y
CONFIG_EEPROM_93CX6=y
CONFIG_SCSI=y
# CONFIG_SCSI_MQ_DEFAULT is not set
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SENSORS_TSL2550=m
+CONFIG_BMP085_I2C=m
+CONFIG_SRAM=y
+CONFIG_SENSORS_LIS3_I2C=m
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_VIRTIO=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_VIRTIO_NET=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+CONFIG_DM9000=y
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_TI_DAVINCI_EMAC=y
CONFIG_TI_CPSW=y
+CONFIG_TI_CPTS=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_AT803X_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
@@ -257,16 +375,49 @@ CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_OHCI_HCD=m
CONFIG_USB_KC2190=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
+CONFIG_USB_CDC_PHONET=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_DEBUG=y
+CONFIG_WL_TI=y
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=m
+CONFIG_KEYBOARD_ATKBD=m
+CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_TWL4030=y
+CONFIG_KEYBOARD_OMAP4=m
+CONFIG_KEYBOARD_TWL4030=m
+# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007=m
+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_TWL4030_PWRBUTTON=y
+CONFIG_INPUT_TPS65218_PWRBUTTON=m
+CONFIG_INPUT_TWL4030_PWRBUTTON=m
+CONFIG_INPUT_PALMAS_PWRBUTTON=m
+CONFIG_SERIO=m
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -276,30 +427,79 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_OMAP=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SPI_OMAP24XX=y
CONFIG_SPI_PL022=y
+CONFIG_SPI_TI_QSPI=m
+CONFIG_HSI=m
+CONFIG_OMAP_SSI=m
+CONFIG_NOKIA_MODEM=m
+CONFIG_SSI_PROTOCOL=m
CONFIG_PINCTRL_SINGLE=y
+CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCA953X=m
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TWL4030=y
CONFIG_POWER_SUPPLY=y
+CONFIG_GPIO_PALMAS=y
+CONFIG_W1=m
+CONFIG_HDQ_MASTER_OMAP=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_CHARGER_ISP1704=m
+CONFIG_CHARGER_TWL4030=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_POWER_RESET=y
+CONFIG_POWER_AVS=y
+CONFIG_HWMON=m
+CONFIG_SENSORS_GPIO_FAN=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_THERMAL=m
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_TI_SOC_THERMAL=m
+CONFIG_TI_THERMAL=y
+CONFIG_OMAP4_THERMAL=y
+CONFIG_OMAP5_THERMAL=y
+CONFIG_DRA752_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_SOFT_WATCHDOG=m
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
+CONFIG_OMAP_WATCHDOG=m
+CONFIG_TWL4030_WATCHDOG=m
CONFIG_MFD_PALMAS=y
CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65218=y
CONFIG_MFD_TPS65910=y
CONFIG_MFD_TWL4030_AUDIO=y
+CONFIG_MFD_TI_AM335X_TSCADC=m
CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PBIAS=y
+CONFIG_REGULATOR_TI_ABB=y
+CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_DRM=y
@@ -308,15 +508,55 @@ CONFIG_DRM_OMAP=y
CONFIG_OMAP2_DSS_DSI=y
CONFIG_DRM_TILCDC=y
CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
+CONFIG_OMAP2_DSS=m
+CONFIG_OMAP5_DSS_HDMI=y
+CONFIG_OMAP2_DSS_SDI=y
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_FB_OMAP2=m
+CONFIG_DISPLAY_ENCODER_TFP410=m
+CONFIG_DISPLAY_ENCODER_TPD12S015=m
+CONFIG_DISPLAY_CONNECTOR_DVI=m
+CONFIG_DISPLAY_CONNECTOR_HDMI=m
+CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m
+CONFIG_DISPLAY_PANEL_DPI=m
+CONFIG_DISPLAY_PANEL_DSI_CM=m
+CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m
+CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m
+CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m
+CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m
+CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_PANDORA=m
+CONFIG_BACKLIGHT_GPIO=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=m
+CONFIG_SND_EDMA_SOC=m
+CONFIG_SND_AM33XX_SOC_EVM=m
+CONFIG_SND_DAVINCI_SOC_MCASP=m
+CONFIG_SND_OMAP_SOC=m
+CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
+CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
+CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -324,22 +564,79 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_MUSB_DSPS=y
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_HID_GENERIC=m
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+CONFIG_USB=m
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=m
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_WDM=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_OMAP2PLUS=m
+CONFIG_USB_MUSB_AM35X=m
+CONFIG_USB_MUSB_DSPS=m
+CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_TI_CPPI41_DMA=y
CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_DWC3=m
+CONFIG_USB_TEST=m
CONFIG_AM335X_PHY_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_PHONET=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_G_NOKIA=m
CONFIG_MMC=y
CONFIG_SDIO_UART=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_TWL4030=y
CONFIG_RTC_DRV_PALMAS=y
CONFIG_RTC_DRV_OMAP=y
CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_PALMAS=m
+CONFIG_RTC_DRV_TWL92330=y
+CONFIG_RTC_DRV_TWL4030=m
+CONFIG_RTC_DRV_OMAP=m
CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
CONFIG_VIRTIO_BALLOON=y
@@ -348,6 +645,27 @@ CONFIG_VIRTIO_MMIO=y
CONFIG_ARM_TIMER_SP804=y
CONFIG_EXTCON_PALMAS=y
CONFIG_OMAP_USB2=y
+CONFIG_TI_EDMA=y
+CONFIG_DMA_OMAP=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXTCON=m
+CONFIG_EXTCON_USB_GPIO=m
+CONFIG_EXTCON_PALMAS=m
+CONFIG_TI_EMIF=m
+CONFIG_IIO=m
+CONFIG_TI_AM335X_ADC=m
+CONFIG_PWM=y
+CONFIG_PWM_TIECAP=m
+CONFIG_PWM_TIEHRPWM=m
+CONFIG_PWM_TWL=m
+CONFIG_PWM_TWL_LED=m
+CONFIG_PHY_DM816X_USB=m
+CONFIG_OMAP_USB2=m
+CONFIG_TI_PIPE3=y
+CONFIG_TWL4030_USB=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
@@ -355,12 +673,20 @@ CONFIG_EXT4_ENCRYPTION=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
+CONFIG_FANOTIFY=y
+CONFIG_QUOTA=y
+CONFIG_QFMT_V2=y
+CONFIG_AUTOFS4_FS=m
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_ROMFS_FS=m
+CONFIG_CONFIGFS_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
@@ -405,6 +731,13 @@ CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_ENCRYPTED_KEYS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_PROVE_LOCKING=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_SECURITY=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_XCBC=m
@@ -419,6 +752,12 @@ CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
--
2.20.1


--
Quirin Gylstorff

Siemens AG
Corporate Technology
Research in Digitalization and Automation
Smart Embedded Systems
CT RDA IOT SES-DE
Otto-Hahn-Ring 6
81739 Muenchen, Germany
Mobile: +49 173 3746683
mailto:quirin.gylstorff@siemens.com
www.siemens.com/ingenuityforlife

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Hagemann Snabe; Managing Board: Joe Kaeser, Chairman, President and
Chief Executive Officer; Roland Busch, Lisa Davis, Klaus Helmrich,
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and Munich, Germany; Commercial registries: Berlin Charlottenburg, HRB
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[ANNOUNCE] Release v4.19.144-cip34 and v4.4.235-cip49

Nobuhiro Iwamatsu
 

Hi,

I was late for release due to a LAVA issue.
(Thanks to Chris for fixing this.)

CIP kernel team has released Linux kernel v4.19.144-cip34 and v4.4.235-cip49.
The linux-4.19.y-cip has been updated base version from v4.19.140 to v4.19.144,
and The linux-4.4.y-cip tree has been updated base version from
v4.4.231 to v4.4.235.

This release includes many backport patches for each version.
4.19.y-cip adds a new revision board for HiHope RZ/G2M and many IP support patches
for r8a774e1 and r8a7795. And 4.4.y-cip has added support for Renesas ARM SoC RZ/G1H
(r8a7742) and iWave G21D-Q7 board. Also, the cpufreq driver for TI
platforms (am33xx and etc) has been backported.

We can get this release via the git tree at:

v4.19.144-cip34:
repository:
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git

branch:
linux-4.19.y-cip

commit hash:
1d9c4c7e291d5f49ab07402ef739f98fac6e7adb

added commits:
CIP: Bump version suffix to -cip34 after merge from stable
arm64: dts: renesas: Fix SD Card/eMMC interface device node names
arm64: dts: renesas: r8a774e1: Add RWDT node
dt-bindings: watchdog: renesas,wdt: Document r8a774e1 support
arm64: dts: renesas: r8a774e1: Add MSIOF nodes
spi: renesas,sh-msiof: Add r8a774e1 support
arm64: dts: renesas: r8a774e1: Add I2C and IIC-DVFS support
dt-bindings: i2c: renesas,iic: Document r8a774e1 support
dt-bindings: i2c: renesas,i2c: Document r8a774e1 support
arm64: dts: renesas: r8a774e1: Add SDHI nodes
mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support
arm64: dts: renesas: r8a774e1: Add SCIF and HSCIF nodes
arm64: dts: renesas: r8a774e1: Add CAN[FD] support
can: rcar_can: Remove unused platform data support
arm64: dts: renesas: r8a774e1: Add TMU device nodes
arm64: dts: renesas: r8a774e1: Add CMT device nodes
arm64: dts: renesas: r8a774e1: Add RZ/G2H thermal support
thermal: rcar_gen3_thermal: Add r8a774e1 support
thermal/drivers/rcar_gen3: Fix undefined temperature if negative
thermal: rcar_gen3_thermal: Generate interrupt when temperature changes
thermal: rcar_gen3_thermal: Remove temperature bound
arm64: dts: renesas: r8a774e1: Add operating points
arm64: dts: renesas: r8a774e1: Add Ethernet AVB node
arm64: dts: renesas: r8a774e1: Add GPIO device nodes
arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes
dt-bindings: dma: renesas,rcar-dmac: Document R8A774E1 bindings
arm64: dts: renesas: r8a774e1: Add IPMMU device nodes
iommu/ipmmu-vmsa: Hook up R8A774E1 DT matching code
dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support
arm64: dts: renesas: Add HiHope RZ/G2H sub board support
arm64: dts: renesas: Add HiHope RZ/G2H main board support
dt-bindings: arm: renesas: Add HopeRun RZ/G2H boards
arm64: dts: renesas: Initial r8a774e1 SoC device tree
pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 PFC support
dt-bindings: pinctrl: sh-pfc: Document r8a774e1 PFC support
pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers
pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3
pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3
pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pins
pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pins
pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions
pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions
pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions
pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups
pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias control
arm64: defconfig: Enable R8A774E1 SoC
clk: renesas: cpg-mssr: Add r8a774e1 support
dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
clk: renesas: rzg2: Mark RWDT clocks as critical
clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
clk: renesas: Add r8a774e1 CPG Core Clock Definitions
clk: renesas: rcar-gen3: Add RPC clocks
soc: renesas: rcar-rst: Add support for RZ/G2H
dt-bindings: reset: rcar-rst: Document r8a774e1 reset module
soc: renesas: Identify RZ/G2H
dt-bindings: arm: renesas: Document RZ/G2H SoC DT bindings
soc: renesas: Add Renesas R8A774E1 config option
soc: renesas: rcar-sysc: Add r8a774e1 support
dt-bindings: power: renesas,rcar-sysc: Document r8a774e1 SYSC binding
dt-bindings: power: Add r8a774e1 SYSC power domain definitions
arm64: dts: renesas: r8a774a1: Remove audio port node
arm64: dts: renesas: Add HiHope RZ/G2N Rev2.0/3.0/4.0 board with idk-1110wr display
arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 sub board support
arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 main board support
arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 board with idk-1110wr display
arm64: dts: renesas: hihope-rzg2-ex: Separate out lvds specific nodes into common file
arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 sub board support
arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 main board support
arm64: dts: renesas: Add HiHope RZ/G2M[N] Rev.3.0/4.0 specific into common file
arm64: dts: renesas: hihope-common: Separate out Rev.2.0 specific into hihope-rev2.dtsi file
arm64: dts: renesas: r8a774b1-hihope-rzg2n[-ex]: Rename HiHope RZ/G2N boards
arm64: dts: renesas: r8a774a1-hihope-rzg2m[-ex/-ex-idk-1110wr]: Rename HiHope RZ/G2M boards

v4.4.235-cip49:
repository:
https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git

branch:
linux-4.4.y-cip

commit hash:
c9f71781108017f6e3fc8d3326cf24bb234b5399

added commits:
CIP: Bump version suffix to -cip49 after merge from stable
ARM: dts: am33xx: Add updated operating-points-v2 table for cpu
ARM: omap2plus_defconfig: Enable support for ti-cpufreq
cpufreq: dt: Don't use generic platdev driver for ti-cpufreq platforms
cpufreq: ti-cpufreq: Fix an incorrect error return value
cpufreq: ti-cpufreq: add missing of_node_put()
cpufreq: ti-cpufreq: kfree opp_data when failure
cpufreq: ti: Fix 'of_node_put' being called twice in error handling path
cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime
Documentation: dt: add bindings for ti-cpufreq
PM / OPP: Expose _of_get_opp_desc_node as dev_pm_opp API
PM / OPP: Parse clock-latency and voltage-tolerance for v1 bindings
ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add device tree for camera DB
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
ARM: dts: r8a7742: Drop undocumented compatible string from scifa2 node
ARM: dts: r8a7742: Add Ether support
sh_eth: Add compatible string for R8A7742 SoC
dt-bindings: net: renesas,ether: Document R8A7742 SoC
gpio: rcar: Avoid NULL pointer access in gpio_rcar_set_multiple()
of: Add missing exports of node name compare functions
ARM: dts: r8a7742-iwg21d-q7: Enable cmt0
ARM: dts: r8a7742: Add MSIOF[0123] support
spi: renesas,sh-msiof: Add r8a7742 support
ARM: dts: r8a7742: Add CMT SoC specific support
ARM: dts: r8a7742: Add thermal device to DT
dt-bindings: thermal: rcar-thermal: Add device tree support for r8a7742
ARM: dts: r8a7742-iwg21d-q7: Add RWDT support
ARM: dts: r8a7742: Add RWDT node
dt-bindings: watchdog: renesas,wdt: Document r8a7742 support
ARM: dts: renesas: Fix SD Card/eMMC interface device node names
ARM: dts: r8a7742-iwg21d-q7: Enable SDHI2 controller
ARM: dts: r8a7742: Add MMC0 node
ARM: dts: r8a7742: Add SDHI nodes
dt-bindings: mmc: renesas,sdhi: Document r8a7742 support
ARM: dts: r8a7742: Add APMU nodes
dt-bindings: power: renesas,apmu: Document r8a7742 support
ARM: dts: r8a7742-iwg21d-q7: Enable Ethernet AVB
ARM: dts: r8a7742: Add Ethernet AVB support
dt-bindings: net: renesas, ravb: Add support for r8a7742 SoC
ARM: dts: r8a7742: Add I2C and IIC support
dt-bindings: i2c: renesas, iic: Document r8a7742 support
dt-bindings: i2c: renesas, i2c: Document r8a7742 support
ARM: dts: r8a7742: Add IRQC support
dt-bindings: irqchip: renesas-irqc: Document r8a7742 bindings
ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board
ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM
ARM: dts: r8a7742: Add GPIO nodes
dt-bindings: gpio: renesas, rcar-gpio: Add r8a7742 (RZ/G1H) support
ARM: dts: r8a7742: Initial SoC device tree
pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support
pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group
pinctrl: sh-pfc: r8a7790: Add SCIF_CLK support
pinctrl: sh-pfc: r8a7790: Use PINMUX_SINGLE() instead of raw PINMUX_DATA()
dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support
dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings
dt-bindings: serial: renesas,hscif: Document r8a7742 bindings
dt-bindings: serial: renesas,scifb: Document r8a7742 bindings
dt-bindings: serial: renesas,scif: Document r8a7742 bindings
dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
ARM: multi_v7_defconfig: Enable r8a7742 SoC
ARM: shmobile: defconfig: Enable r8a7742 SoC
ARM: debug-ll: Add support for r8a7742
soc: renesas: Add Renesas R8A7742 config option
ARM: shmobile: r8a7742: Basic SoC support
clk: shmobile: Compile clk-rcar-gen2.c when using the r8a7742
clk: shmobile: Document r8a7742 CPG DIV6 clock support
clk: shmobile: Document r8a7742 MSTP clock support
clk: shmobile: Document r8a7742 CPG clock support
ARM: shmobile: r8a7742: Add clock index macros for DT sources
soc: renesas: rcar-rst: Add support for RZ/G1H
dt-bindings: reset: rcar-rst: Document r8a7742 reset module
ARM: shmobile: Document RZ/G1H SoC DT binding

Best regards,
Nobuhiro


Re: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: Pavel Machek [mailto:pavel@denx.de]
Sent: Monday, September 14, 2020 6:11 AM
To: iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT) <nobuhiro1.iwamatsu@toshiba.co.jp>
Cc: biju.das.jz@bp.renesas.com; cip-dev@lists.cip-project.org; pavel@denx.de; chris.paterson2@renesas.com;
prabhakar.mahadev-lad.rj@bp.renesas.com
Subject: Re: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support

Hi!

This patch series add audio support for iWave RZ/G1H board based on
r8a7742 SoC to 4.4.y-cip kernel. All patches in this series
are cherry-picked from mainline.

Lad Prabhakar (4):
dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support
ARM: dts: r8a7742: Add audio support
ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS

.../bindings/sound/renesas,rsnd.txt | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++
arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++
3 files changed, 373 insertions(+)
I reviewd this patch series.
Looks good to me. If If no objection, I will apply and push this.
And I am testing on https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/188827239.
Looks good to me, too. I have no objections.
Thanks! I applied and pushed.

Best regards,
Nobuhiro


Re: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support

Pavel Machek
 

Hi!

This patch series add audio support for iWave RZ/G1H board based on
r8a7742 SoC to 4.4.y-cip kernel. All patches in this series
are cherry-picked from mainline.

Lad Prabhakar (4):
dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support
ARM: dts: r8a7742: Add audio support
ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS

.../bindings/sound/renesas,rsnd.txt | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++
arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++
3 files changed, 373 insertions(+)
I reviewd this patch series.
Looks good to me. If If no objection, I will apply and push this.
And I am testing on https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/188827239.
Looks good to me, too. I have no objections.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support

Nobuhiro Iwamatsu
 

Hi Biju,

-----Original Message-----
From: Biju Das [mailto:biju.das.jz@bp.renesas.com]
Sent: Friday, September 11, 2020 9:32 PM
To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
<nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>; Biju Das <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad
<prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support

This patch series add audio support for iWave RZ/G1H board based on
r8a7742 SoC to 4.4.y-cip kernel. All patches in this series
are cherry-picked from mainline.

Lad Prabhakar (4):
dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support
ARM: dts: r8a7742: Add audio support
ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS

.../bindings/sound/renesas,rsnd.txt | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++
arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++
3 files changed, 373 insertions(+)
I reviewd this patch series.
Looks good to me. If If no objection, I will apply and push this.
And I am testing on https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/188827239.

Best regards,
Nobuhiro


[isar-cip-core][PATCH] swupdate: Clean up do_prepare_build

Jan Kiszka
 

From: Jan Kiszka <jan.kiszka@siemens.com>

Reformat and drop the unused DEBDIR var (which wouldn't work anyway due
to DEBDIR definition in Isar's bitbake.conf)

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
recipes-core/swupdate/swupdate.bb | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/recipes-core/swupdate/swupdate.bb b/recipes-core/swupdate/swupdate.bb
index 95cf73a..dd02cc2 100644
--- a/recipes-core/swupdate/swupdate.bb
+++ b/recipes-core/swupdate/swupdate.bb
@@ -39,16 +39,14 @@ TEMPLATE_FILES = "debian/changelog.tmpl debian/control.tmpl debian/rules.tmpl"
TEMPLATE_VARS += "BUILD_DEB_DEPENDS DEFCONFIG DEBIAN_DEPENDS"

do_prepare_build() {
- DEBDIR=${S}/debian
- cp -R ${WORKDIR}/debian ${S}
-
- install -m 0644 ${WORKDIR}/${PN}.cfg ${S}/swupdate.cfg
- install -m 0644 ${WORKDIR}/${DEFCONFIG}.gen ${S}/configs/${DEFCONFIG}
-
- if ! grep -q "configs/${DEFCONFIG}" ${S}/.gitignore
- then
- echo "configs/${DEFCONFIG}" >> ${S}/.gitignore
- fi
- # luahandler
- install -m 0644 ${WORKDIR}/${SWUPDATE_LUASCRIPT} ${S}
+ cp -R ${WORKDIR}/debian ${S}
+
+ install -m 0644 ${WORKDIR}/${PN}.cfg ${S}/swupdate.cfg
+ install -m 0644 ${WORKDIR}/${DEFCONFIG}.gen ${S}/configs/${DEFCONFIG}
+
+ if ! grep -q "configs/${DEFCONFIG}" ${S}/.gitignore; then
+ echo "configs/${DEFCONFIG}" >> ${S}/.gitignore
+ fi
+ # luahandler
+ install -m 0644 ${WORKDIR}/${SWUPDATE_LUASCRIPT} ${S}
}
--
2.26.2


[PATCH 4.4.y-cip 4/4] ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS

Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit fc3a1b2763d44ed471169e1dff2c8ce0fb352c1c upstream.

Enable sound with DMA support on carrier board.

DMA transfer uses DVC

DMA DMApp
[MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI]

DMA DMApp
[MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI]

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1590611013-26029-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 63 +++++++++++++++++++++++++
1 file changed, 63 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 8085e1651493..428c494d88a3 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -5,6 +5,29 @@
* Copyright (C) 2020 Renesas Electronics Corp.
*/

+/*
+ * SSI-SGTL5000
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
/dts-v1/;
#include "r8a7742-iwg21m.dtsi"

@@ -36,6 +59,21 @@
regulator-always-on;
};

+ rsnd_sgtl5000: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
+
vcc_sdhi2: regulator-vcc-sdhi2 {
compatible = "regulator-fixed";

@@ -117,6 +155,27 @@
function = "sdhi2";
power-source = <3300>;
};
+
+ sound_pins: sound {
+ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
+ function = "ssi";
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi4 &src4 &dvc1>;
+ capture = <&ssi3 &src3 &dvc0>;
+ };
+ };
};

&rwdt {
@@ -141,3 +200,7 @@
wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+&ssi4 {
+ shared-pin;
+};
--
2.17.1


[PATCH 4.4.y-cip 3/4] ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec

Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 436765010f266a2afd6c9afd15233225448a3e8d upstream.

This patch enables SGTL5000 audio codec on the carrier board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1590611013-26029-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +++++++++++++++++++++++++
1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 1c7e58d47d73..8085e1651493 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -22,6 +22,20 @@
stdout-path = "serial2:115200n8";
};

+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ reg_1p5v: 1p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
vcc_sdhi2: regulator-vcc-sdhi2 {
compatible = "regulator-fixed";

@@ -60,6 +74,24 @@
};
};

+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&audio_clock>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ VDDD-supply = <&reg_1p5v>;
+ };
+};
+
&cmt0 {
status = "okay";
};
@@ -70,6 +102,11 @@
function = "avb";
};

+ i2c2_pins: i2c2 {
+ groups = "i2c2_b";
+ function = "i2c2";
+ };
+
scifa2_pins: scifa2 {
groups = "scifa2_data_c";
function = "scifa2";
--
2.17.1


[PATCH 4.4.y-cip 2/4] ARM: dts: r8a7742: Add audio support

Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 3816124fd0408ec98773409732035f8f8425ff50 upstream.

Add sound support for the RZ/G1H SoC (a.k.a. R8A7742).

This work is based on similar work done on the R8A7744 SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/1590526904-13855-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: changed clocks and power-domain properties, removed resets property]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 272 +++++++++++++++++++++++++++++++++
1 file changed, 272 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 32ed4138dc1b..e37f65655479 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -14,6 +14,27 @@
#address-cells = <2>;
#size-cells = <2>;

+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -1180,6 +1201,257 @@
status = "disabled";
};

+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7742",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&mstp10_clks R8A7742_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7742_CLK_SSI9>, <&mstp10_clks R8A7742_CLK_SSI8>,
+ <&mstp10_clks R8A7742_CLK_SSI7>, <&mstp10_clks R8A7742_CLK_SSI6>,
+ <&mstp10_clks R8A7742_CLK_SSI5>, <&mstp10_clks R8A7742_CLK_SSI4>,
+ <&mstp10_clks R8A7742_CLK_SSI3>, <&mstp10_clks R8A7742_CLK_SSI2>,
+ <&mstp10_clks R8A7742_CLK_SSI1>, <&mstp10_clks R8A7742_CLK_SSI0>,
+ <&mstp10_clks R8A7742_CLK_SCU_SRC9>, <&mstp10_clks R8A7742_CLK_SCU_SRC8>,
+ <&mstp10_clks R8A7742_CLK_SCU_SRC7>, <&mstp10_clks R8A7742_CLK_SCU_SRC6>,
+ <&mstp10_clks R8A7742_CLK_SCU_SRC5>, <&mstp10_clks R8A7742_CLK_SCU_SRC4>,
+ <&mstp10_clks R8A7742_CLK_SCU_SRC3>, <&mstp10_clks R8A7742_CLK_SCU_SRC2>,
+ <&mstp10_clks R8A7742_CLK_SCU_SRC1>, <&mstp10_clks R8A7742_CLK_SCU_SRC0>,
+ <&mstp10_clks R8A7742_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7742_CLK_SCU_CTU1_MIX1>,
+ <&mstp10_clks R8A7742_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7742_CLK_SCU_CTU1_MIX1>,
+ <&mstp10_clks R8A7742_CLK_SCU_DVC0>, <&mstp10_clks R8A7742_CLK_SCU_DVC1>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&m2_clk>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&cpg_clocks>;
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>,
+ <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>,
+ <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>,
+ <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>,
+ <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>,
+ <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+ <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+ <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>,
+ <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>,
+ <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>,
+ <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&mstp5_clks R8A7742_CLK_AUDIO_DMAC0>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&mstp5_clks R8A7742_CLK_AUDIO_DMAC1>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
--
2.17.1


[PATCH 4.4.y-cip 1/4] dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support

Biju Das <biju.das.jz@...>
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit b6f10d3f2e6dfccf58c54e81c8af586b66a80ce4 upstream.

Document RZ/G1H (R8A7742) SoC bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1590526904-13855-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
index 23656d187f3a..bf07aa156a6a 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -6,6 +6,7 @@ Required properties:
"renesas,rcar_sound-gen2" if generation2 (or RZ/G1)
"renesas,rcar_sound-gen3" if generation3
Examples with soctypes are:
+ - "renesas,rcar_sound-r8a7742" (RZ/G1H)
- "renesas,rcar_sound-r8a7743" (RZ/G1M)
- "renesas,rcar_sound-r8a7744" (RZ/G1N)
- "renesas,rcar_sound-r8a7745" (RZ/G1E)
--
2.17.1


[PATCH 4.4.y-cip 0/4] Add RZ/G1H Audio support

Biju Das <biju.das.jz@...>
 

This patch series add audio support for iWave RZ/G1H board based on
r8a7742 SoC to 4.4.y-cip kernel. All patches in this series
are cherry-picked from mainline.

Lad Prabhakar (4):
dt-bindings: ASoC: renesas,rsnd: Add r8a7742 support
ARM: dts: r8a7742: Add audio support
ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS

.../bindings/sound/renesas,rsnd.txt | 1 +
arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 100 +++++++
arch/arm/boot/dts/r8a7742.dtsi | 272 ++++++++++++++++++
3 files changed, 373 insertions(+)

--
2.17.1


Re: CIP IRC weekly meeting today

Nobuhiro Iwamatsu
 

Hi Kudo-san,

Sorry, I can not join IRC meeting today.

-----Original Message-----
From: cip-dev@lists.cip-project.org [mailto:cip-dev@lists.cip-project.org] On Behalf Of
masashi.kudo@cybertrust.co.jp
Sent: Thursday, September 10, 2020 9:23 AM
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] CIP IRC weekly meeting today

Hi all,

Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.

*Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting from the first week of Apr. according
to TSC meeting*
https://www.timeanddate.com/worldclock/meetingdetails.html?year=2020&month=9&day=10&hour=9&min=0&sec=0&p1=224&p2=
179&p3=136&p4=37&p5=241&p6=248

USWest USEast UK DE TW JP
02:00 05:00 10:00 11:00 17:00 18:00

Channel:
* irc:chat.freenode.net:6667/cip

Last meeting minutes:
https://irclogs.baserock.org/meetings/cip/2020/09/cip.2020-09-03-09.00.log.html

Agenda:

* Action item
1. Combine root filesystem with kselftest binary - iwamatsu
No update.

2. Post LTP results to KernelCI - patersonc

* Kernel maintenance updates
I reviewed and pushed patches in cip-dev.

* Kernel testing
* Software update
* CIP Security
* AOB

The meeting will take 30 min, although it can be extended to an hour if it makes sense and those involved in the topics
can stay. Otherwise, the topic will be taken offline or in the next meeting.

Best regards,
Best regards,
Nobuhiro


CIP IRC weekly meeting today

masashi.kudo@cybertrust.co.jp <masashi.kudo@...>
 

Hi all,

Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today.

*Please note that the IRC meeting was rescheduled to UTC (GMT) 09:00 starting from the first week of Apr. according to TSC meeting*
https://www.timeanddate.com/worldclock/meetingdetails.html?year=2020&month=9&day=10&hour=9&min=0&sec=0&p1=224&p2=179&p3=136&p4=37&p5=241&p6=248

USWest USEast UK DE TW JP
02:00 05:00 10:00 11:00 17:00 18:00

Channel:
* irc:chat.freenode.net:6667/cip

Last meeting minutes:
https://irclogs.baserock.org/meetings/cip/2020/09/cip.2020-09-03-09.00.log.html

Agenda:

* Action item
1. Combine root filesystem with kselftest binary - iwamatsu
2. Post LTP results to KernelCI - patersonc

* Kernel maintenance updates
* Kernel testing
* Software update
* CIP Security
* AOB

The meeting will take 30 min, although it can be extended to an hour if it makes sense and those involved in the topics can stay. Otherwise, the topic will be taken offline or in the next meeting.

Best regards,
--
M. Kudo
Cybertrust Japan Co., Ltd.


Re: [PATCH 4.4.y-cip 00/11] ti-cpufreq backport

Nobuhiro Iwamatsu
 

Hi,

-----Original Message-----
From: Pavel Machek [mailto:pavel@denx.de]
Sent: Wednesday, September 9, 2020 4:04 PM
To: Chen-Yu Tsai (Moxa) <wens@csie.org>
Cc: iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT) <nobuhiro1.iwamatsu@toshiba.co.jp>; pavel@denx.de;
cip-dev@lists.cip-project.org; JohnsonCH.Chen@moxa.com; victor.yu@moxa.com
Subject: Re: [PATCH 4.4.y-cip 00/11] ti-cpufreq backport

Hi!

This is the final part of MOXA's PM / OPP / ti-cpufreq backport series.
Part 2, which consisted of OPP / cpufreq-dt cleanups, is abandoned in
favor of directly backporting the ti-cpufreq driver.

This part includes a couple of patches to the PM / OPP subsystem to
expose required APIs, and deal with the v1/v2 mixed OPP table used
by am33xx. The rest are the backport of the ti-cpufreq driver, and
fixes for this driver. The fixes were requested by CIP kernel
maintainers as part of MOXA's previous attempt to backport ti-cpufreq.
They are included as separate patches, as there are quite a few of them
spread over multiple kernel releases.

The result is that my BeagleBone Black can run at higher speeds than
without the ti-cpufreq driver due to having a better silicon
revision.
The series looks good to me. I can apply it if it passes testing and
there are no other comments.
This patch series looks good to me too.
So, I applied and pushed.


Best regards,
Pavel
Best regards,
Nobuhiro


Re: [PATCH 4.4.y-cip 0/6] RZ/G1H add support for Ether/[H]SCIF{A|B}

Pavel Machek
 

Hi!

This patch series adds support for ETHER/[H]SCIF{A|B} to
R8A7742 SoC and alongside adds camera daughter board dts
which fits on iwg21d-q7 development platform.

Patches 1/6, 3/6, 5/6, 6/6 have been cherry picked from
upstream kernel, patch 2/6 is a hookup patch to enable
eth on R8A7742 SoC and patch 4/6 is a fixup patch.
This series looks okay to me.
Thank you, applied and pushed out.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.4.y-cip 00/11] ti-cpufreq backport

Pavel Machek
 

Hi!

This is the final part of MOXA's PM / OPP / ti-cpufreq backport series.
Part 2, which consisted of OPP / cpufreq-dt cleanups, is abandoned in
favor of directly backporting the ti-cpufreq driver.

This part includes a couple of patches to the PM / OPP subsystem to
expose required APIs, and deal with the v1/v2 mixed OPP table used
by am33xx. The rest are the backport of the ti-cpufreq driver, and
fixes for this driver. The fixes were requested by CIP kernel
maintainers as part of MOXA's previous attempt to backport ti-cpufreq.
They are included as separate patches, as there are quite a few of them
spread over multiple kernel releases.

The result is that my BeagleBone Black can run at higher speeds than
without the ti-cpufreq driver due to having a better silicon
revision.
The series looks good to me. I can apply it if it passes testing and
there are no other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 4.4.y-cip 04/11] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime

Pavel Machek
 

Hi!

+ ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
+ if (ret)
+ goto fail_put_node;
+
+ of_node_put(opp_data->opp_node);
+
+ ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
+ version, VERSION_COUNT));
+ if (ret) {
+ dev_err(opp_data->cpu_dev,
+ "Failed to set supported hardware\n");
+ goto fail_put_node;
+ }
of_node_put() is done twice in the last error path.
Aha, it is fixed in subsequent patches. Sorry for the noise.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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