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[PATCH 5.10.y-cip 08/24] clk: renesas: r9a07g044: Fix P1 Clock
Lad Prabhakar
From: Biju Das <biju.das.jz@...>
commit fd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a upstream. As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4. So fix the clock definitions for P1. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- drivers/clk/renesas/r9a07g044-cpg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index d5803fb1242e..d895c1cef1fa 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -30,8 +30,8 @@ enum clk_ids { CLK_PLL2_DIV20, CLK_PLL3, CLK_PLL3_DIV2, + CLK_PLL3_DIV2_4, CLK_PLL3_DIV4, - CLK_PLL3_DIV8, CLK_PLL4, CLK_PLL5, CLK_PLL5_DIV2, @@ -67,15 +67,15 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), - DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8), /* Core output clk */ DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), - DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), }; -- 2.17.1
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[PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Rename divider table
Lad Prabhakar
From: Biju Das <biju.das.jz@...>
commit e93c1373613fb2f3e59db5f13271f155820e6a67 upstream. As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it can be reused. Signed-off-by: Biju Das <biju.das.jz@...> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- drivers/clk/renesas/r9a07g044-cpg.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 50b5269586a4..d5803fb1242e 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -42,12 +42,13 @@ enum clk_ids { }; /* Divider tables */ -static const struct clk_div_table dtable_3b[] = { +static const struct clk_div_table dtable_1_32[] = { {0, 1}, {1, 2}, {2, 4}, {3, 8}, {4, 32}, + {0, 0}, }; static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { @@ -72,10 +73,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { /* Core output clk */ DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, - dtable_3b, CLK_DIVIDER_HIWORD_MASK), + dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, - DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), + DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), }; static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { -- 2.17.1
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[PATCH 5.10.y-cip 06/24] clk: renesas: Add support for R9A07G044 SoC
Lad Prabhakar
commit 17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5 upstream.
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@...>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g044-cpg.c | 127 ++++++++++++++++++++++++ drivers/clk/renesas/renesas-rzg2l-cpg.c | 6 ++ drivers/clk/renesas/renesas-rzg2l-cpg.h | 2 + 5 files changed, 141 insertions(+) create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index b0c938b5243c..4d8de55bc6f4 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -32,6 +32,7 @@ config CLK_RENESAS select CLK_R8A77995 if ARCH_R8A77995 select CLK_R8A779A0 if ARCH_R8A779A0 select CLK_R9A06G032 if ARCH_R9A06G032 + select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -155,6 +156,10 @@ config CLK_R9A06G032 help This is a driver for R9A06G032 clocks +config CLK_R9A07G044 + bool "RZ/G2L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 24bdfb7bc342..077fae8b0846 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o +obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c new file mode 100644 index 000000000000..50b5269586a4 --- /dev/null +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L CPG driver + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/kernel.h> + +#include <dt-bindings/clock/r9a07g044-cpg.h> + +#include "renesas-rzg2l-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A07G044_OSCCLK, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_OSC_DIV1000, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL2_DIV16, + CLK_PLL2_DIV20, + CLK_PLL3, + CLK_PLL3_DIV2, + CLK_PLL3_DIV4, + CLK_PLL3_DIV8, + CLK_PLL4, + CLK_PLL5, + CLK_PLL5_DIV2, + CLK_PLL6, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_3b[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {4, 32}, +}; + +static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), + + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), + DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), + + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), + DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8), + + /* Core output clk */ + DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), + DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, + dtable_3b, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, + DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), +}; + +static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { + DEF_MOD("gic", R9A07G044_CLK_GIC600, + R9A07G044_CLK_P1, + 0x514, BIT(0), (BIT(0) | BIT(1))), + DEF_MOD("ia55", R9A07G044_CLK_IA55, + R9A07G044_CLK_P1, + 0x518, (BIT(0) | BIT(1)), BIT(0)), + DEF_MOD("scif0", R9A07G044_CLK_SCIF0, + R9A07G044_CLK_P0, + 0x584, BIT(0), BIT(0)), + DEF_MOD("scif1", R9A07G044_CLK_SCIF1, + R9A07G044_CLK_P0, + 0x584, BIT(1), BIT(1)), + DEF_MOD("scif2", R9A07G044_CLK_SCIF2, + R9A07G044_CLK_P0, + 0x584, BIT(2), BIT(2)), + DEF_MOD("scif3", R9A07G044_CLK_SCIF3, + R9A07G044_CLK_P0, + 0x584, BIT(3), BIT(3)), + DEF_MOD("scif4", R9A07G044_CLK_SCIF4, + R9A07G044_CLK_P0, + 0x584, BIT(4), BIT(4)), + DEF_MOD("sci0", R9A07G044_CLK_SCI0, + R9A07G044_CLK_P0, + 0x588, BIT(0), BIT(0)), +}; + +static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + R9A07G044_CLK_GIC600, +}; + +const struct rzg2l_cpg_info r9a07g044_cpg_info = { + /* Core Clocks */ + .core_clks = r9a07g044_core_clks, + .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a07g044_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a07g044_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), + .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1, +}; diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c index cc2842d31a71..5009b9e48b13 100644 --- a/drivers/clk/renesas/renesas-rzg2l-cpg.c +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c @@ -723,6 +723,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) } static const struct of_device_id rzg2l_cpg_match[] = { +#ifdef CONFIG_CLK_R9A07G044 + { + .compatible = "renesas,r9a07g044-cpg", + .data = &r9a07g044_cpg_info, + }, +#endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/renesas-rzg2l-cpg.h index 8ff0047ffeb9..3948bdd8afc9 100644 --- a/drivers/clk/renesas/renesas-rzg2l-cpg.h +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h @@ -131,4 +131,6 @@ struct rzg2l_cpg_info { unsigned int num_crit_mod_clks; }; +extern const struct rzg2l_cpg_info r9a07g044_cpg_info; + #endif -- 2.17.1
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[PATCH 5.10.y-cip 05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC
Lad Prabhakar
commit ef3c613ccd68a78727b817c3dacf4a68d1ffc67f upstream.
Add CPG core wrapper for RZ/G2L family. Based on a patch in the BSP by Binh Nguyen <binh.nguyen.jz@...>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/renesas-rzg2l-cpg.c | 744 ++++++++++++++++++++++++ drivers/clk/renesas/renesas-rzg2l-cpg.h | 134 +++++ 4 files changed, 883 insertions(+) create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.c create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.h diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 18915d668a30..b0c938b5243c 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -177,6 +177,10 @@ config CLK_RCAR_USB2_CLOCK_SEL help This is a driver for R-Car USB2 clock selector +config CLK_RZG2L + bool "Renesas RZ/G2L family clock support" if COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index c803912ef2ce..24bdfb7bc342 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o +obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o # Generic obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c new file mode 100644 index 000000000000..cc2842d31a71 --- /dev/null +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2L Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * Based on renesas-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2013 Ideas On Board SPRL + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clk/renesas.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_domain.h> +#include <linux/reset-controller.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +#include "renesas-rzg2l-cpg.h" + +#ifdef DEBUG +#define WARN_DEBUG(x) WARN_ON(x) +#else +#define WARN_DEBUG(x) do { } while (0) +#endif + +#define DIV_RSMASK(v, s, m) ((v >> s) & m) +#define GET_SHIFT(val) ((val >> 12) & 0xff) +#define GET_WIDTH(val) ((val >> 8) & 0xf) + +#define KDIV(val) DIV_RSMASK(val, 16, 0xffff) +#define MDIV(val) DIV_RSMASK(val, 6, 0x3ff) +#define PDIV(val) DIV_RSMASK(val, 0, 0x3f) +#define SDIV(val) DIV_RSMASK(val, 0, 0x7) + +#define CLK_ON_R(reg) (reg) +#define CLK_MON_R(reg) (0x680 - 0x500 + (reg)) +#define CLK_RST_R(reg) (0x800 - 0x500 + (reg)) +#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg)) + +#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff) +#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff) +#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff) + +/** + * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data + * + * @rcdev: Reset controller entity + * @dev: CPG device + * @base: CPG register block base address + * @rmw_lock: protects register accesses + * @clks: Array containing all Core and Module Clocks + * @num_core_clks: Number of Core Clocks in clks[] + * @num_mod_clks: Number of Module Clocks in clks[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @notifiers: Notifier chain to save/restore clock state for system resume + * @info: Pointer to platform data + */ +struct rzg2l_cpg_priv { + struct reset_controller_dev rcdev; + struct device *dev; + void __iomem *base; + spinlock_t rmw_lock; + + struct clk **clks; + unsigned int num_core_clks; + unsigned int num_mod_clks; + unsigned int last_dt_core_clk; + + struct raw_notifier_head notifiers; + const struct rzg2l_cpg_info *info; +}; + +static void rzg2l_cpg_del_clk_provider(void *data) +{ + of_clk_del_provider(data); +} + +static struct clk * __init +rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, + struct clk **clks, + void __iomem *base, + struct rzg2l_cpg_priv *priv) +{ + struct device *dev = priv->dev; + const struct clk *parent; + const char *parent_name; + struct clk_hw *clk_hw; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + if (core->dtable) + clk_hw = clk_hw_register_divider_table(dev, core->name, + parent_name, 0, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, + core->dtable, + &priv->rmw_lock); + else + clk_hw = clk_hw_register_divider(dev, core->name, + parent_name, 0, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, &priv->rmw_lock); + + if (IS_ERR(clk_hw)) + return NULL; + + return clk_hw->clk; +} + +struct pll_clk { + struct clk_hw hw; + unsigned int conf; + unsigned int type; + void __iomem *base; + struct rzg2l_cpg_priv *priv; +}; + +#define to_pll(_hw) container_of(_hw, struct pll_clk, hw) + +static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk = to_pll(hw); + struct rzg2l_cpg_priv *priv = pll_clk->priv; + unsigned int val1, val2; + unsigned int mult = 1; + unsigned int div = 1; + + if (pll_clk->type != CLK_TYPE_SAM_PLL) + return parent_rate; + + val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); + val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); + mult = MDIV(val1) + KDIV(val1) / 65536; + div = PDIV(val1) * (1 << SDIV(val2)); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); +} + +static const struct clk_ops rzg2l_cpg_pll_ops = { + .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate, +}; + +static struct clk * __init +rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, + struct clk **clks, + void __iomem *base, + struct rzg2l_cpg_priv *priv) +{ + struct device *dev = priv->dev; + const struct clk *parent; + struct clk_init_data init; + const char *parent_name; + struct pll_clk *pll_clk; + struct clk *clk; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) { + clk = ERR_PTR(-ENOMEM); + return NULL; + } + + parent_name = __clk_get_name(parent); + init.name = core->name; + init.ops = &rzg2l_cpg_pll_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll_clk->hw.init = &init; + pll_clk->conf = core->conf; + pll_clk->base = base; + pll_clk->priv = priv; + pll_clk->type = core->type; + + clk = clk_register(NULL, &pll_clk->hw); + if (IS_ERR(clk)) + kfree(pll_clk); + + return clk; +} + +static struct clk +*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int clkidx = clkspec->args[1]; + struct rzg2l_cpg_priv *priv = data; + struct device *dev = priv->dev; + const char *type; + struct clk *clk; + + switch (clkspec->args[0]) { + case CPG_CORE: + type = "core"; + if (clkidx > priv->last_dt_core_clk) { + dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); + return ERR_PTR(-EINVAL); + } + clk = priv->clks[clkidx]; + break; + + case CPG_MOD: + type = "module"; + if (clkidx > priv->num_mod_clks) { + dev_err(dev, "Invalid %s clock index %u\n", type, + clkidx); + return ERR_PTR(-EINVAL); + } + clk = priv->clks[priv->num_core_clks + clkidx]; + break; + + default: + dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); + return ERR_PTR(-EINVAL); + } + + if (IS_ERR(clk)) + dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, + PTR_ERR(clk)); + else + dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", + clkspec->args[0], clkspec->args[1], clk, + clk_get_rate(clk)); + return clk; +} + +static void __init +rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, + const struct rzg2l_cpg_info *info, + struct rzg2l_cpg_priv *priv) +{ + struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent; + struct device *dev = priv->dev; + unsigned int id = core->id, div = core->div; + const char *parent_name; + + WARN_DEBUG(id >= priv->num_core_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + + if (!core->name) { + /* Skip NULLified clock */ + return; + } + + switch (core->type) { + case CLK_TYPE_IN: + clk = of_clk_get_by_name(priv->dev->of_node, core->name); + break; + case CLK_TYPE_FF: + WARN_DEBUG(core->parent >= priv->num_core_clks); + parent = priv->clks[core->parent]; + if (IS_ERR(parent)) { + clk = parent; + goto fail; + } + + parent_name = __clk_get_name(parent); + clk = clk_register_fixed_factor(NULL, core->name, + parent_name, CLK_SET_RATE_PARENT, + core->mult, div); + break; + case CLK_TYPE_SAM_PLL: + clk = rzg2l_cpg_pll_clk_register(core, priv->clks, + priv->base, priv); + break; + case CLK_TYPE_DIV: + clk = rzg2l_cpg_div_clk_register(core, priv->clks, + priv->base, priv); + break; + default: + goto fail; + }; + + if (IS_ERR_OR_NULL(clk)) + goto fail; + + dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); + priv->clks[id] = clk; + return; + +fail: + dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", + core->name, PTR_ERR(clk)); +} + +/** + * struct mstp_clock - MSTP gating clock + * + * @hw: handle between common and hardware-specific interfaces + * @off: register offset + * @onoff: ON/MON bits + * @reset: reset bits + * @priv: CPG/MSTP private data + */ +struct mstp_clock { + struct clk_hw hw; + u16 off; + u8 onoff; + u8 reset; + struct rzg2l_cpg_priv *priv; +}; + +#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw) + +static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) +{ + struct mstp_clock *clock = to_mod_clock(hw); + struct rzg2l_cpg_priv *priv = clock->priv; + unsigned int reg = clock->off; + struct device *dev = priv->dev; + unsigned long flags; + unsigned int i; + u32 value; + + if (!clock->off) { + dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk); + return 0; + } + + dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, + enable ? "ON" : "OFF"); + spin_lock_irqsave(&priv->rmw_lock, flags); + + if (enable) + value = (clock->onoff << 16) | clock->onoff; + else + value = clock->onoff << 16; + writel(value, priv->base + CLK_ON_R(reg)); + + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (!enable) + return 0; + + for (i = 1000; i > 0; --i) { + if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff)) + break; + cpu_relax(); + } + + if (!i) { + dev_err(dev, "Failed to enable CLK_ON %p\n", + priv->base + CLK_ON_R(reg)); + return -ETIMEDOUT; + } + + return 0; +} + +static int rzg2l_mod_clock_enable(struct clk_hw *hw) +{ + return rzg2l_mod_clock_endisable(hw, true); +} + +static void rzg2l_mod_clock_disable(struct clk_hw *hw) +{ + rzg2l_mod_clock_endisable(hw, false); +} + +static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) +{ + struct mstp_clock *clock = to_mod_clock(hw); + struct rzg2l_cpg_priv *priv = clock->priv; + u32 value; + + if (!clock->off) { + dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk); + return 1; + } + + value = readl(priv->base + CLK_MON_R(clock->off)); + + return !(value & clock->onoff); +} + +static const struct clk_ops rzg2l_mod_clock_ops = { + .enable = rzg2l_mod_clock_enable, + .disable = rzg2l_mod_clock_disable, + .is_enabled = rzg2l_mod_clock_is_enabled, +}; + +static void __init +rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, + const struct rzg2l_cpg_info *info, + struct rzg2l_cpg_priv *priv) +{ + struct mstp_clock *clock = NULL; + struct device *dev = priv->dev; + unsigned int id = mod->id; + struct clk_init_data init; + struct clk *parent, *clk; + const char *parent_name; + unsigned int i; + + WARN_DEBUG(id < priv->num_core_clks); + WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + + if (!mod->name) { + /* Skip NULLified clock */ + return; + } + + parent = priv->clks[mod->parent]; + if (IS_ERR(parent)) { + clk = parent; + goto fail; + } + + clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); + if (!clock) { + clk = ERR_PTR(-ENOMEM); + goto fail; + } + + init.name = mod->name; + init.ops = &rzg2l_mod_clock_ops; + init.flags = CLK_SET_RATE_PARENT; + for (i = 0; i < info->num_crit_mod_clks; i++) + if (id == info->crit_mod_clks[i]) { + dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n", + mod->name); + init.flags |= CLK_IS_CRITICAL; + break; + } + + parent_name = __clk_get_name(parent); + init.parent_names = &parent_name; + init.num_parents = 1; + + clock->off = mod->off; + clock->onoff = mod->onoff; + clock->reset = mod->reset; + clock->priv = priv; + clock->hw.init = &init; + + clk = clk_register(NULL, &clock->hw); + if (IS_ERR(clk)) + goto fail; + + dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); + priv->clks[id] = clk; + return; + +fail: + dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", + mod->name, PTR_ERR(clk)); + kfree(clock); +} + +#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev) + +static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 dis = info->mod_clks[id].reset; + u32 we = dis << 16; + + dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n", + info->mod_clks[id].name, id, CLK_RST_R(reg)); + + /* Reset module */ + writel(we, priv->base + CLK_RST_R(reg)); + + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + + /* Release module from reset state */ + writel(we | dis, priv->base + CLK_RST_R(reg)); + + return 0; +} + +static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 value = info->mod_clks[id].reset << 16; + + dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n", + info->mod_clks[id].name, id, CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); + return 0; +} + +static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 dis = info->mod_clks[id].reset; + u32 value = (dis << 16) | dis; + + dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n", + info->mod_clks[id].name, id, CLK_RST_R(reg)); + + writel(value, priv->base + CLK_RST_R(reg)); + return 0; +} + +static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); + const struct rzg2l_cpg_info *info = priv->info; + unsigned int reg = info->mod_clks[id].off; + u32 bitmask = info->mod_clks[id].reset; + + return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); +} + +static const struct reset_control_ops rzg2l_cpg_reset_ops = { + .reset = rzg2l_cpg_reset, + .assert = rzg2l_cpg_assert, + .deassert = rzg2l_cpg_deassert, + .status = rzg2l_cpg_status, +}; + +static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int id = reset_spec->args[0]; + + if (id >= rcdev->nr_resets) { + dev_err(rcdev->dev, "Invalid reset index %u\n", id); + return -EINVAL; + } + + return id; +} + +static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) +{ + priv->rcdev.ops = &rzg2l_cpg_reset_ops; + priv->rcdev.of_node = priv->dev->of_node; + priv->rcdev.dev = priv->dev; + priv->rcdev.of_reset_n_cells = 1; + priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate; + priv->rcdev.nr_resets = priv->num_mod_clks; + + return devm_reset_controller_register(priv->dev, &priv->rcdev); +} + +static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec) +{ + if (clkspec->args_count != 2) + return false; + + switch (clkspec->args[0]) { + case CPG_MOD: + return true; + + default: + return false; + } +} + +static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev) +{ + struct device_node *np = dev->of_node; + struct of_phandle_args clkspec; + struct clk *clk; + int error; + int i = 0; + + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, + &clkspec)) { + if (rzg2l_cpg_is_pm_clk(&clkspec)) + goto found; + + of_node_put(clkspec.np); + i++; + } + + return 0; + +found: + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + + if (IS_ERR(clk)) + return PTR_ERR(clk); + + error = pm_clk_create(dev); + if (error) + goto fail_put; + + error = pm_clk_add_clk(dev, clk); + if (error) + goto fail_destroy; + + return 0; + +fail_destroy: + pm_clk_destroy(dev); +fail_put: + clk_put(clk); + return error; +} + +static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev) +{ + if (!pm_clk_no_clocks(dev)) + pm_clk_destroy(dev); +} + +static int __init rzg2l_cpg_add_clk_domain(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct generic_pm_domain *genpd; + + genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = np->name; + genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | + GENPD_FLAG_ACTIVE_WAKEUP; + genpd->attach_dev = rzg2l_cpg_attach_dev; + genpd->detach_dev = rzg2l_cpg_detach_dev; + pm_genpd_init(genpd, &pm_domain_always_on_gov, false); + + of_genpd_add_provider_simple(np, genpd); + return 0; +} + +static int __init rzg2l_cpg_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct rzg2l_cpg_info *info; + struct rzg2l_cpg_priv *priv; + unsigned int nclks, i; + struct clk **clks; + int error; + + info = of_device_get_match_data(dev); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->info = info; + spin_lock_init(&priv->rmw_lock); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + nclks = info->num_total_core_clks + info->num_hw_mod_clks; + clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->clks = clks; + priv->num_core_clks = info->num_total_core_clks; + priv->num_mod_clks = info->num_hw_mod_clks; + priv->last_dt_core_clk = info->last_dt_core_clk; + + for (i = 0; i < nclks; i++) + clks[i] = ERR_PTR(-ENOENT); + + for (i = 0; i < info->num_core_clks; i++) + rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv); + + for (i = 0; i < info->num_mod_clks; i++) + rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv); + + error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv); + if (error) + return error; + + error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np); + if (error) + return error; + + error = rzg2l_cpg_add_clk_domain(dev); + if (error) + return error; + + error = rzg2l_cpg_reset_controller_register(priv); + if (error) + return error; + + return 0; +} + +static const struct of_device_id rzg2l_cpg_match[] = { + { /* sentinel */ } +}; + +static struct platform_driver rzg2l_cpg_driver = { + .driver = { + .name = "rzg2l-cpg", + .of_match_table = rzg2l_cpg_match, + }, +}; + +static int __init rzg2l_cpg_init(void) +{ + return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe); +} + +subsys_initcall(rzg2l_cpg_init); + +MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/renesas-rzg2l-cpg.h new file mode 100644 index 000000000000..8ff0047ffeb9 --- /dev/null +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G2L Clock Pulse Generator + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __RENESAS_RZG2L_CPG_H__ +#define __RENESAS_RZG2L_CPG_H__ + +#define CPG_PL2_DDIV (0x204) +#define CPG_PL3A_DDIV (0x208) + +/* n = 0/1/2 for PLL1/4/6 */ +#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) +#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) + +#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) + +#define DDIV_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) +#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) +#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) + +/** + * Definitions of CPG Core Clocks + * + * These include: + * - Clock outputs exported to DT + * - External input clocks + * - Internal CPG clocks + */ +struct cpg_core_clk { + const char *name; + unsigned int id; + unsigned int parent; + unsigned int div; + unsigned int mult; + unsigned int type; + unsigned int conf; + const struct clk_div_table *dtable; + const char * const *parent_names; + int flag; + int num_parents; +}; + +enum clk_types { + /* Generic */ + CLK_TYPE_IN, /* External Clock Input */ + CLK_TYPE_FF, /* Fixed Factor Clock */ + CLK_TYPE_SAM_PLL, + + /* Clock with divider */ + CLK_TYPE_DIV, +}; + +#define DEF_TYPE(_name, _id, _type...) \ + { .name = _name, .id = _id, .type = _type } +#define DEF_BASE(_name, _id, _type, _parent...) \ + DEF_TYPE(_name, _id, _type, .parent = _parent) +#define DEF_SAMPLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) +#define DEF_INPUT(_name, _id) \ + DEF_TYPE(_name, _id, CLK_TYPE_IN) +#define DEF_FIXED(_name, _id, _parent, _mult, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) +#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ + .parent = _parent, .dtable = _dtable, .flag = _flag) + +/** + * struct rzg2l_mod_clk - Module Clocks definitions + * + * @name: handle between common and hardware-specific interfaces + * @id: clock index in array containing all Core and Module Clocks + * @parent: id of parent clock + * @off: register offset + * @onoff: ON/MON bits + * @reset: reset bits + */ +struct rzg2l_mod_clk { + const char *name; + unsigned int id; + unsigned int parent; + u16 off; + u8 onoff; + u8 reset; +}; + +#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \ + [_id] = { \ + .name = _name, \ + .id = MOD_CLK_BASE + _id, \ + .parent = (_parent), \ + .off = (_off), \ + .onoff = (_onoff), \ + .reset = (_reset) \ + } + +/** + * struct rzg2l_cpg_info - SoC-specific CPG Description + * + * @core_clks: Array of Core Clock definitions + * @num_core_clks: Number of entries in core_clks[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @num_total_core_clks: Total number of Core Clocks (exported + internal) + * + * @mod_clks: Array of Module Clock definitions + * @num_mod_clks: Number of entries in mod_clks[] + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware + * + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that + * should not be disabled without a knowledgeable driver + * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + */ +struct rzg2l_cpg_info { + /* Core Clocks */ + const struct cpg_core_clk *core_clks; + unsigned int num_core_clks; + unsigned int last_dt_core_clk; + unsigned int num_total_core_clks; + + /* Module Clocks */ + const struct rzg2l_mod_clk *mod_clks; + unsigned int num_mod_clks; + unsigned int num_hw_mod_clks; + + /* Critical Module Clocks that should not be disabled */ + const unsigned int *crit_mod_clks; + unsigned int num_crit_mod_clks; +}; + +#endif -- 2.17.1
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[PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC
Lad Prabhakar
From: Biju Das <biju.das.jz@...>
commit 3b2cd60689fa439481f535ee4463fb223a276f43 upstream. Add serial support for RZ/G2L SoC with earlycon and extended mode register support. Signed-off-by: Biju Das <biju.das.jz@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Link: https://lore.kernel.org/r/20210603221758.10305-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- drivers/tty/serial/sh-sci.c | 12 +++++++++++- drivers/tty/serial/sh-sci.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index f700bfaef129..c3fd49480ad3 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -289,7 +289,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { }, /* - * The "SCIFA" that is in RZ/T and RZ/A2. + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. * It looks like a normal SCIF with FIFO data, but with a * compressed address space. Also, the break out of interrupts * are different: ERI/BRI, RXI, TXI, TEI, DRI. @@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { [SCFDR] = { 0x0E, 16 }, [SCSPTR] = { 0x10, 16 }, [SCLSR] = { 0x12, 16 }, + [SEMR] = { 0x14, 8 }, }, .fifosize = 16, .overrun_reg = SCLSR, @@ -2527,6 +2528,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_cflag & PARENB) bits++; + if (sci_getreg(port, SEMR)->size) + serial_port_out(port, SEMR, 0); + if (best_clk >= 0) { if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) switch (srr + 1) { @@ -3194,6 +3198,10 @@ static const struct of_device_id of_sci_match[] = { .compatible = "renesas,scif-r7s9210", .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), }, + { + .compatible = "renesas,scif-r9a07g044", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), + }, /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3476,6 +3484,7 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device, port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; return early_console_setup(device, PORT_SCIF); } + static int __init scifa_early_console_setup(struct earlycon_device *device, const char *opt) { @@ -3495,6 +3504,7 @@ static int __init hscif_early_console_setup(struct earlycon_device *device, OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index c0dfe4382898..c0ae78632dda 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -31,6 +31,7 @@ enum { SCCKS, /* BRG Clock Select Register */ HSRTRGR, /* Rx FIFO Data Count Trigger Register */ HSTTRGR, /* Tx FIFO Data Count Trigger Register */ + SEMR, /* Serial extended mode register */ SCIx_NR_REGS, }; -- 2.17.1
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[PATCH 5.10.y-cip 04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
Lad Prabhakar
commit 403921373799a133e41b59cb730e2c4239663f51 upstream.
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 8.3 ("Clock List") of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das <biju.das.jz@...> Link: https://lore.kernel.org/r/20210609153230.6967-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- include/dt-bindings/clock/r9a07g044-cpg.h | 89 +++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h new file mode 100644 index 000000000000..1d8986563fc5 --- /dev/null +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G044 CPG Core Clocks */ +#define R9A07G044_CLK_I 0 +#define R9A07G044_CLK_I2 1 +#define R9A07G044_CLK_G 2 +#define R9A07G044_CLK_S0 3 +#define R9A07G044_CLK_S1 4 +#define R9A07G044_CLK_SPI0 5 +#define R9A07G044_CLK_SPI1 6 +#define R9A07G044_CLK_SD0 7 +#define R9A07G044_CLK_SD1 8 +#define R9A07G044_CLK_M0 9 +#define R9A07G044_CLK_M1 10 +#define R9A07G044_CLK_M2 11 +#define R9A07G044_CLK_M3 12 +#define R9A07G044_CLK_M4 13 +#define R9A07G044_CLK_HP 14 +#define R9A07G044_CLK_TSU 15 +#define R9A07G044_CLK_ZT 16 +#define R9A07G044_CLK_P0 17 +#define R9A07G044_CLK_P1 18 +#define R9A07G044_CLK_P2 19 +#define R9A07G044_CLK_AT 20 +#define R9A07G044_OSCCLK 21 + +/* R9A07G044 Module Clocks */ +#define R9A07G044_CLK_GIC600 0 +#define R9A07G044_CLK_IA55 1 +#define R9A07G044_CLK_SYC 2 +#define R9A07G044_CLK_DMAC 3 +#define R9A07G044_CLK_SYSC 4 +#define R9A07G044_CLK_MTU 5 +#define R9A07G044_CLK_GPT 6 +#define R9A07G044_CLK_ETH0 7 +#define R9A07G044_CLK_ETH1 8 +#define R9A07G044_CLK_I2C0 9 +#define R9A07G044_CLK_I2C1 10 +#define R9A07G044_CLK_I2C2 11 +#define R9A07G044_CLK_I2C3 12 +#define R9A07G044_CLK_SCIF0 13 +#define R9A07G044_CLK_SCIF1 14 +#define R9A07G044_CLK_SCIF2 15 +#define R9A07G044_CLK_SCIF3 16 +#define R9A07G044_CLK_SCIF4 17 +#define R9A07G044_CLK_SCI0 18 +#define R9A07G044_CLK_SCI1 19 +#define R9A07G044_CLK_GPIO 20 +#define R9A07G044_CLK_SDHI0 21 +#define R9A07G044_CLK_SDHI1 22 +#define R9A07G044_CLK_USB0 23 +#define R9A07G044_CLK_USB1 24 +#define R9A07G044_CLK_CANFD 25 +#define R9A07G044_CLK_SSI0 26 +#define R9A07G044_CLK_SSI1 27 +#define R9A07G044_CLK_SSI2 28 +#define R9A07G044_CLK_SSI3 29 +#define R9A07G044_CLK_MHU 30 +#define R9A07G044_CLK_OSTM0 31 +#define R9A07G044_CLK_OSTM1 32 +#define R9A07G044_CLK_OSTM2 33 +#define R9A07G044_CLK_WDT0 34 +#define R9A07G044_CLK_WDT1 35 +#define R9A07G044_CLK_WDT2 36 +#define R9A07G044_CLK_WDT_PON 37 +#define R9A07G044_CLK_GPU 38 +#define R9A07G044_CLK_ISU 39 +#define R9A07G044_CLK_H264 40 +#define R9A07G044_CLK_CRU 41 +#define R9A07G044_CLK_MIPI_DSI 42 +#define R9A07G044_CLK_LCDC 43 +#define R9A07G044_CLK_SRC 44 +#define R9A07G044_CLK_RSPI0 45 +#define R9A07G044_CLK_RSPI1 46 +#define R9A07G044_CLK_RSPI2 47 +#define R9A07G044_CLK_ADC 48 +#define R9A07G044_CLK_TSU_PCLK 49 +#define R9A07G044_CLK_SPI 50 +#define R9A07G044_CLK_MIPI_DSI_V 51 +#define R9A07G044_CLK_MIPI_DSI_PIN 52 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ -- 2.17.1
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[PATCH 5.10.y-cip 03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
Lad Prabhakar
commit f8ec89126a72b399e63399d8d21fd413f4059f00 upstream.
Document the device tree bindings of the Renesas RZ/G2L SoC clock driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das <biju.das.jz@...> Reviewed-by: Rob Herring <robh@...> Link: https://lore.kernel.org/r/20210609153230.6967-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml new file mode 100644 index 000000000000..30b2e3d0d25d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode + +maintainers: + - Geert Uytterhoeven <geert+renesas@...> + +description: | + On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module + Standby Mode share the same register block. + + They provide the following functionalities: + - The CPG block generates various core clocks, + - The Module Standby Mode block provides two functions: + 1. Module Standby, providing a Clock Domain to control the clock supply + to individual SoC devices, + 2. Reset Control, to perform a software reset of individual SoC devices. + +properties: + compatible: + const: renesas,r9a07g044-cpg # RZ/G2{L,LC} + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: + Clock source to CPG can be either from external clock input (EXCLK) or + crystal oscillator (XIN/XOUT). + const: extal + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + <dt-bindings/clock/r9a07g044-cpg.h> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>. + const: 2 + + '#power-domain-cells': + description: + SoC devices that are part of the CPG/Module Standby Mode Clock Domain and + can be power-managed through Module Standby should refer to the CPG device + node in their "power-domains" property, as documented by the generic PM + Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the module number, as defined in + the <dt-bindings/clock/r9a07g044-cpg.h>. + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g044-cpg"; + reg = <0x11010000 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; -- 2.17.1
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[PATCH 5.10.y-cip 01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings
Lad Prabhakar
commit 92e06e12212abe4b27ff18445a0f88e6b5236331 upstream.
Document R9A07G044 SoC variants, common compatiable string "renesas,scif-r9a07g044" is added for RZ/G2L and RZ/G2LC SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> Reviewed-by: Biju Das <biju.das.jz@...> Acked-by: Rob Herring <robh@...> Link: https://lore.kernel.org/r/20210514192218.13022-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@...> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index eda3d2c6bdd3..7fa8cb0a7769 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -63,6 +63,10 @@ properties: - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 - const: renesas,scif # generic SCIF compatible UART + - items: + - enum: + - renesas,scif-r9a07g044 # RZ/G2{L,LC} + reg: maxItems: 1 -- 2.17.1
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[PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK
Lad Prabhakar
Hi All,
This patch series adds the following: * Serial support * Clock support * Initial RZ/G2L SoC DTSI - CPU - CPG - GIC * Initial device tree for RZ/G2L SMARC EVK - memory - External input clock - SCIF All the patches have been cherry picked from 5.16-rc5. For testing purpose MR [0] can be used. [0] https://gitlab.com/cip-project/cip-kernel/ cip-kernel-config/-/merge_requests/52 Cheers, Prabhakar Biju Das (9): serial: sh-sci: Add support for RZ/G2L SoC clk: renesas: r9a07g044: Rename divider table clk: renesas: r9a07g044: Fix P1 Clock clk: renesas: r9a07g044: Add P2 Clock support clk: renesas: rzg2l: Add multi clock PM support dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions clk: renesas: rzg2l: Add support to handle MUX clocks clk: renesas: rzg2l: Add support to handle coupled clocks clk: renesas: rzg2l: Fix clk status function Dan Carpenter (2): clk: renesas: rzg2l: Fix a double free on error clk: renesas: rzg2l: Avoid mixing error pointers and NULL Dmitry Baryshkov (1): clk: mux: provide devm_clk_hw_register_mux() Geert Uytterhoeven (1): clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] Lad Prabhakar (9): dt-bindings: serial: renesas,scif: Document r9a07g044 bindings dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver dt-bindings: clock: Add r9a07g044 CPG Clock Definitions clk: renesas: Add CPG core wrapper for RZ/G2L SoC clk: renesas: Add support for R9A07G044 SoC arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK arm64: dts: renesas: r9a07g044: Add SYSC node clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() Yang Li (2): clk: renesas: rzg2l: Remove unneeded semicolon clk: renesas: rzg2l: Fix return value and unused assignment .../bindings/clock/renesas,rzg2l-cpg.yaml | 83 ++ .../bindings/serial/renesas,scif.yaml | 4 + arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 132 +++ arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 + .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 + arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi | 13 + arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 + drivers/clk/clk-mux.c | 35 + drivers/clk/renesas/Kconfig | 9 + drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r9a07g044-cpg.c | 142 +++ drivers/clk/renesas/rzg2l-cpg.c | 844 ++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 176 ++++ drivers/tty/serial/sh-sci.c | 12 +- drivers/tty/serial/sh-sci.h | 1 + include/dt-bindings/clock/r9a07g044-cpg.h | 219 +++++ include/linux/clk-provider.h | 13 + 18 files changed, 1759 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c create mode 100644 drivers/clk/renesas/rzg2l-cpg.c create mode 100644 drivers/clk/renesas/rzg2l-cpg.h create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h -- 2.17.1
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cip/linux-5.10.y-cip baseline: 137 runs, 1 regressions (v5.10.83-cip1-7-geb3270fae08d)
#kernelci
kernelci.org bot <bot@...>
cip/linux-5.10.y-cip baseline: 137 runs, 1 regressions (v5.10.83-cip1-7-geb3270fae08d)
Regressions Summary ------------------- platform | arch | lab | compiler | defconfig | regressions -------------------------+--------+---------------+----------+------------------------------+------------ minnowboard-turbot-E3826 | x86_64 | lab-collabora | gcc-10 | x86_64_defcon...6-chromebook | 1 Details: https://kernelci.org/test/job/cip/branch/linux-5.10.y-cip/kernel/v5.10.83-cip1-7-geb3270fae08d/plan/baseline/ Test: baseline Tree: cip Branch: linux-5.10.y-cip Describe: v5.10.83-cip1-7-geb3270fae08d URL: https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git SHA: eb3270fae08d8e549e33314d589f9153d60ce4a6 Test Regressions ---------------- platform | arch | lab | compiler | defconfig | regressions -------------------------+--------+---------------+----------+------------------------------+------------ minnowboard-turbot-E3826 | x86_64 | lab-collabora | gcc-10 | x86_64_defcon...6-chromebook | 1 Details: https://kernelci.org/test/plan/id/61bb1820e5b9921a2c397174 Results: 0 PASS, 1 FAIL, 0 SKIP Full config: x86_64_defconfig+x86-chromebook Compiler: gcc-10 (gcc (Debian 10.2.1-6) 10.2.1 20210110) Plain log: https://storage.kernelci.org//cip/linux-5.10.y-cip/v5.10.83-cip1-7-geb3270fae08d/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/lab-collabora/baseline-minnowboard-turbot-E3826.txt HTML log: https://storage.kernelci.org//cip/linux-5.10.y-cip/v5.10.83-cip1-7-geb3270fae08d/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/lab-collabora/baseline-minnowboard-turbot-E3826.html Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20211210.0/x86/rootfs.cpio.gz * baseline.login: https://kernelci.org/test/case/id/61bb1820e5b9921a2c397175 new failure (last pass: v5.10.8-8301-g3d6168cb89f6)
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cip/linux-5.10.y-cip build: 175 builds: 3 failed, 172 passed, 4 errors, 10 warnings (v5.10.83-cip1-7-geb3270fae08d)
#kernelci
kernelci.org bot <bot@...>
cip/linux-5.10.y-cip build: 175 builds: 3 failed, 172 passed, 4 errors, 10 warnings (v5.10.83-cip1-7-geb3270fae08d)
Full Build Summary: https://kernelci.org/build/cip/branch/linux-5.10.y-cip/kernel/v5.10.83-cip1-7-geb3270fae08d/ Tree: cip Branch: linux-5.10.y-cip Git Describe: v5.10.83-cip1-7-geb3270fae08d Git Commit: eb3270fae08d8e549e33314d589f9153d60ce4a6 Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git Built: 7 unique architectures Build Failures Detected: arm: rpc_defconfig: (gcc-10) FAIL mips: ip27_defconfig: (gcc-10) FAIL ip28_defconfig: (gcc-10) FAIL Errors and Warnings Detected: arc: arm64: arm: rpc_defconfig (gcc-10): 4 errors i386: mips: 32r2el_defconfig (gcc-10): 1 warning decstation_64_defconfig (gcc-10): 1 warning decstation_defconfig (gcc-10): 1 warning decstation_r4k_defconfig (gcc-10): 1 warning lemote2f_defconfig (gcc-10): 1 warning rm200_defconfig (gcc-10): 1 warning riscv: rv32_defconfig (gcc-10): 4 warnings x86_64: Errors summary: 2 arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3m 2 arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’ Warnings summary: 3 kernel/rcu/tasks.h:707:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function] 2 <stdin>:830:2: warning: #warning syscall fstat64 not implemented [-Wcpp] 2 <stdin>:1127:2: warning: #warning syscall fstatat64 not implemented [-Wcpp] 1 net/mac80211/mlme.c:4328:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=] 1 drivers/block/paride/bpck.c:32: warning: "PC" redefined 1 WARNING: modpost: Symbol info of vmlinux is missing. Unresolved symbol check will be entirely skipped. ================================================================================ Detailed per-defconfig build reports: -------------------------------------------------------------------------------- 32r2el_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches Warnings: WARNING: modpost: Symbol info of vmlinux is missing. Unresolved symbol check will be entirely skipped. -------------------------------------------------------------------------------- allnoconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- allnoconfig (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- allnoconfig (i386, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- am200epdkit_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ar7_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- aspeed_g4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- assabet_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- at91_dt_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ath25_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- axm55xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- axs103_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- axs103_smp_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- badge4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- bcm2835_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- bcm47xx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- bcm63xx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- bigsur_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- bmips_stb_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- capcella_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- cavium_octeon_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- cerfcube_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ci20_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- cm_x300_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- cobalt_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- colibri_pxa270_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- colibri_pxa300_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- collie_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- corgi_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- cu1000-neo_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- cu1830-neo_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- davinci_all_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- db1xxx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- decstation_64_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches Warnings: kernel/rcu/tasks.h:707:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function] -------------------------------------------------------------------------------- decstation_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches Warnings: kernel/rcu/tasks.h:707:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function] -------------------------------------------------------------------------------- decstation_r4k_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches Warnings: kernel/rcu/tasks.h:707:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function] -------------------------------------------------------------------------------- defconfig (riscv, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- defconfig (arm64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- defconfig+kselftest (arm64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- dove_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- e55_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ebsa110_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- efm32_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ep93xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- eseries_pxa_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- exynos_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ezx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- footbridge_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- fuloong2e_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- gcw0_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- gemini_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- gpr_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- h3600_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- h5000_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- hackkit_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- haps_hs_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- haps_hs_smp_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- hisi_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- hsdk_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- imote2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- imx_v4_v5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- imx_v6_v7_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- integrator_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- iop32x_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ip22_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ip27_defconfig (mips, gcc-10) — FAIL, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ip28_defconfig (mips, gcc-10) — FAIL, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ip32_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- ixp4xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- jazz_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- jmr3927_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- jornada720_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- keystone_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- lart_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- lemote2f_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches Warnings: net/mac80211/mlme.c:4328:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=] -------------------------------------------------------------------------------- loongson1b_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- loongson1c_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- loongson3_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- lpc18xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- lpc32xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- lpd270_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- magician_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mainstone_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- malta_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- malta_kvm_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- malta_kvm_guest_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- malta_qemu_32r6_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- maltaaprp_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- maltasmvp_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- maltasmvp_eva_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- maltaup_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- maltaup_xpa_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- milbeaut_m10v_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mmp2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- moxart_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mpc30x_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mps2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mtx1_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- multi_v4t_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- multi_v5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- multi_v7_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- multi_v7_defconfig+kselftest (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mvebu_v5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mvebu_v7_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- mxs_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- neponset_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- netwinder_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- nhk8815_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- nlm_xlp_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- nlm_xlr_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- nommu_k210_defconfig (riscv, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- nsimosci_hs_smp_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- omap1_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- omap2plus_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- omega2p_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- orion5x_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- oxnas_v6_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- palmz72_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pcm027_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pic32mzda_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pleb_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- prima2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pxa168_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pxa255-idp_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pxa910_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- pxa_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- qcom_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- qi_lb60_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- rb532_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- rbtx49xx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- realview_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- rm200_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches Warnings: drivers/block/paride/bpck.c:32: warning: "PC" redefined -------------------------------------------------------------------------------- rpc_defconfig (arm, gcc-10) — FAIL, 4 errors, 0 warnings, 0 section mismatches Errors: arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3m arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’ arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3m arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’ -------------------------------------------------------------------------------- rs90_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- rt305x_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- rv32_defconfig (riscv, gcc-10) — PASS, 0 errors, 4 warnings, 0 section mismatches Warnings: <stdin>:830:2: warning: #warning syscall fstat64 not implemented [-Wcpp] <stdin>:1127:2: warning: #warning syscall fstatat64 not implemented [-Wcpp] <stdin>:830:2: warning: #warning syscall fstat64 not implemented [-Wcpp] <stdin>:1127:2: warning: #warning syscall fstatat64 not implemented [-Wcpp] -------------------------------------------------------------------------------- s3c2410_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- s5pv210_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- sama5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- sb1250_swarm_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- shannon_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- shmobile_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- simpad_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- socfpga_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- spear13xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- spear6xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- spitz_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- stm32_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- sunxi_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tango4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tb0219_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tb0226_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tb0287_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tct_hammer_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tegra_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tinyconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tinyconfig (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- tinyconfig (i386, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- trizeps4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- u300_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- u8500_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- vdk_hs38_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- vdk_hs38_smp_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- versatile_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- vexpress_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- vf610m4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- vocore2_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- vt8500_v6_v7_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- workpad_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- x86_64_defconfig (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- x86_64_defconfig+kselftest (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- x86_64_defconfig+x86-chromebook (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- x86_64_defconfig+x86-chromebook+kselftest (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- xcep_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- zeus_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches -------------------------------------------------------------------------------- zx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches --- For more info write to <info@...>
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Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Chris Paterson
Hello,
From: nobuhiro1.iwamatsu@...We are planning to propose it as a CIP reference board and we plan to add some hardware to the CIP's LAVA infrastructure. If the board is not accepted as a CIP reference board, we would still like to add support for it in the CIP Kernel as we have done for other non-reference boards such as the iWave RZ/G1E, HiHope RZ/G2H boards etc. Kind regards, Chris
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Re: CIP IRC weekly meeting today on libera.chat
Nobuhiro Iwamatsu
Hi Jan,
I may not be able to attend today for personal reason. So, I'll email my work this week. * Kernel maintenance updates* I released v4.19.220-cip63 and v4.4.294-cip66 * I reviewed 5.10.85. * I reviewed patches for Renesas RZ/G2L SoC. * I am working the systematization of patch reviews. It hasn't worked completely yet, but I think I can report the completion tomorrow. Best regards, Nobuhiro ________________________________________ 差出人: cip-dev@... <cip-dev@...> が Jan Kiszka <jan.kiszka@...> の代理で送信 送信日時: 2021年12月16日 16:40 宛先: cip-dev 件名: [cip-dev] CIP IRC weekly meeting today on libera.chat Hi all, Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today. Our channel is the following: irc:irc.libera.chat:6667/cip The IRC meeting is scheduled to UTC (GMT) 13:00: https://www.timeanddate.com/worldclock/meetingdetails.html?year=2021&month=12&day=16&hour=13&min=0&sec=0&p1=224&p2=179&p3=136&p4=37&p5=241&p6=248 USWest USEast UK DE TW JP 06:00 09:00 13:00 14:00 21:00 22:00 Last meeting minutes: https://irclogs.baserock.org/meetings/cip/2021/12/cip.2021-12-09-13.01.log.html * Action item 1. Combine root filesystem with kselftest binary (finishing) - alicef 2. Propose tweet on KernelCI-CIP collaboration progress - alicef 3. Clarify with KernelCI whether CIP maintainers can get accounts - alicef * Kernel maintenance updates * Kernel testing * AOB Jan
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Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Pavel Machek
Hi!
Looks good to me too. I have series ready due to testing, so I'll pushThis patch series adds initial support for Renesas RZ/G2L SoC [0] and it. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: New CVE entries in this week
Pavel Machek
Hi!
CVE-2021-3864: descendant's dumpable setting with certain SUID binariesThis one is actually quite interesting. Untrusted users should not normally have shell access on embedded systems, but it highlights topic of coredumps. Default config of coredumping is unsuitable for many embedded systems; coredumps should be probably disabled. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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CIP IRC weekly meeting today on libera.chat
Jan Kiszka
Hi all,
Kindly be reminded to attend the weekly meeting through IRC to discuss technical topics with CIP kernel today. Our channel is the following: irc:irc.libera.chat:6667/cip The IRC meeting is scheduled to UTC (GMT) 13:00: https://www.timeanddate.com/worldclock/meetingdetails.html?year=2021&month=12&day=16&hour=13&min=0&sec=0&p1=224&p2=179&p3=136&p4=37&p5=241&p6=248 USWest USEast UK DE TW JP 06:00 09:00 13:00 14:00 21:00 22:00 Last meeting minutes: https://irclogs.baserock.org/meetings/cip/2021/12/cip.2021-12-09-13.01.log.html * Action item 1. Combine root filesystem with kselftest binary (finishing) - alicef 2. Propose tweet on KernelCI-CIP collaboration progress - alicef 3. Clarify with KernelCI whether CIP maintainers can get accounts - alicef * Kernel maintenance updates * Kernel testing * AOB Jan
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Re: New CVE entries in this week
Masami Ichikawa
Hi !
On Thu, Dec 16, 2021 at 2:27 PM Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...> wrote: Thank you. LGTM ! Best regards,Regards, -- Masami Ichikawa Cybertrust Japan Co., Ltd. Email :masami.ichikawa@... :masami.ichikawa@...
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Re: New CVE entries in this week
Nobuhiro Iwamatsu
Hi,
CVE-2021-39648: usb: gadget: configfs: Fix use-after-free issue with udc_nameI created a patch which revise this issue. I attached this mail. Best regards, Nobuhiro ________________________________________ 差出人: cip-dev@... <cip-dev@...> が Masami Ichikawa <masami.ichikawa@...> の代理で送信 送信日時: 2021年12月16日 8:49 宛先: cip-dev 件名: [cip-dev] New CVE entries in this week Hi ! It's this week's CVE report. This week reported ten new CVEs and two of them aren't fixed in the mainline yet. * New CVEs CVE-2021-0961: In quota_proc_write of xt_quota2.c, there is a possible way to read kernel memory due to uninitialized data CVSS v3 score is not provided This bug is fixed in Android kernel. There is three commits to fix this bug. https://android.googlesource.com/kernel/common/+/e113eb454e92 https://android.googlesource.com/kernel/common/+/60a4c35570d9 https://android.googlesource.com/kernel/common/+/4b05a506bda0 These commit modified net/netfilter/xt_quota2.c which is Android specific source. So this CVE is Android specific bug. The mainline and stable kernels aren't affected. Fixed status The mainline and stable kernels aren't affected. CVE-2021-39648: usb: gadget: configfs: Fix use-after-free issue with udc_name CVSS v3 score is not provided 4.4 kernel gadget_dev_desc_UDC_show() is bit different from later kernel versions. However, it looks 4.4 also has same issue. Fixed status mainline: [64e6bbfff52db4bf6785fab9cffab850b2de6870] stable/4.14: [6766064c794afeacc29b21fc09ea4dbe3cae1af3] stable/4.19: [83b74059fdf1c4fa6ed261725e6f301552ad23f7] stable/4.9: [225330e682fa9aaa152287b49dea1ce50fbe0a92] stable/5.10: [a4b202cba3ab1a7a8b1ca92603931fba5e2032c3] stable/5.4: [bcffe2de9dde74174805d5f56a990353e33b8072] CVE-2021-39656: configfs: fix a use-after-free in __configfs_open_file Bug introduced commit b0841ee was merged in 5.3-rc8. This commit isn't backported to 4.4 so 4.4 isn't affected. Fixed status mainline: [14fbbc8297728e880070f7b077b3301a8c698ef9] stable/4.14: [4769013f841ed35bdce3b11b64349d0c166ee0a2] stable/4.19: [9123463620132ada85caf5dc664b168f480b0cc4] stable/4.9: [6f5c47f0faed69f2e78e733fb18261854979e79f] stable/5.10: [109720342efd6ace3d2e8f34a25ea65036bb1d3b] stable/5.4: [73aa6f93e1e980f392b3da4fee830b0e0a4a40ff] CVE-2021-39657: scsi: ufs: Correct the LUN used in eh_device_reset_handler() callback CVSS v3 score is not provided Bug was fixed in 5.11-rc4. so mainline and stable kernels are already fixed. Fixed status mainline: [35fc4cd34426c242ab015ef280853b7bff101f48] stable/4.14: [30f2a89f9481f851bc68e51a1e7114392b052231] stable/4.19: [b397fcae2207963747c6f947ef4d06575553eaef] stable/4.4: [a4cdbf4805bfed8f39e6b25f113588064d9a6ac5] stable/4.9: [7bbac19e604b2443c93f01c3259734d53f776dbf] stable/5.10: [2536194bb3b099cc9a9037009b86e7ccfb81461c] stable/5.4: [97853a7eae80a695a18ce432524eaa7432199a41] CVE-2021-4090: kernel: Overflow of bmval[bmlen-1] in nfsd4_decode_bitmap function CVSS v3 score is not provided OOB write bug in nsfd. This bug was introduced by commit d1c263a ("NFSD: Replace READ* macros in nfsd4_decode_fattr() ") since 5.11-rc1 and fixed in 5.16-rc2. Before 5.11 kernels aren't affected this issue. Fixed status mainline: [c0019b7db1d7ac62c711cda6b357a659d46428fe] stable/5.15: [10c22d9519f3f5939de61a1500aa3a926b778d3a] CVE-2021-4093: KVM: SVM: out-of-bounds read/write in sev_es_string_io CVSS v3 score is not provided OOB read/write bug in AMD SVM mode. This bug was introduced by commit 7ed9abf ("KVM: SVM: Support string IO operations for an SEV-ES guest") which is merged since 5.11-rc1. Before 5.11 kernels aren't affected this issue. Fixed status mainline: [95e16b4792b0429f1933872f743410f00e590c55] CVE-2021-4095: KVM: NULL pointer dereference in kvm_dirty_ring_get() in virt/kvm/dirty_ring.c CVSS v3 score is not provided This issues was introduced by commit 629b534 ("KVM: x86/xen: update wallclock region") which is merged in 5.12-rc1-dontuse. Before 5.12-rc1-dontuse kernels aren't affectd this issue. Patch is being reviewed. Fixed status Not fixed yet. CVE-2021-3864: descendant's dumpable setting with certain SUID binaries CVSS v3 score is not provided This bug is able to write coredump file anyware. However, abusing this bug, such as arbitrary code execution is required some program. The PoC(https://www.openwall.com/lists/oss-security/2021/10/20/2). There is two mitigation techniques are suggested. So, users follow these mitigation technique is recommended. Fixed status Not fixed yet. CVE-2021-4083: fget: check that the fd still exists after getting a ref to it CVSS v3 score is not provided UAF bug in fs/file.c it causes system crash, priviledge escalation. The mainline and all stable kernels are aready fixed. Fixed status mainline: [054aa8d439b9185d4f5eb9a90282d1ce74772969] stable/4.14: [98548c3a9882a1ea993a103be7c1b499f3b88202] stable/4.19: [8bf31f9d9395b71af3ed33166a057cd3ec0c59da] stable/4.4: [8afa4ef999191477506b396fae518338b8996fec] stable/4.9: [a043f5a600052dc93bc3d7a6a2c1592b6ee77482] stable/5.10: [4baba6ba56eb91a735a027f783cc4b9276b48d5b] stable/5.15: [6fe4eadd54da3040cf6f6579ae157ae1395dc0f8] stable/5.4: [03d4462ba3bc8f830d9807e3c3fde54fad06e2e2] CVE-2021-39685: Linux Kernel USB Gadget buffer overflow CVSS v3 score is not provided Buffer overflow bug in USB gadget devices. An attacker can read and/or write up to 65k of kernel memory. It already fixed in mainline and all stable kernels. Fixed status mainline: [153a2d7e3350cc89d406ba2d35be8793a64c2038, 86ebbc11bb3f60908a51f3e41a17e3f477c2eaa3] stable/4.14: [e7c8afee149134b438df153b09af7fd928a8bc24, d8cd524ae4ec788011a14be17503fc224f260fe3] stable/4.19: [13e45e7a262dd96e8161823314679543048709b9, 32de5efd483db68f12233fbf63743a2d92f20ae4] stable/4.4: [93cd7100fe471c5f76fb942358de4ed70dbcaf35, af21211c327c4703c7681fa7286c4d660682e413] stable/4.9: [d2ca6859ea96c6d4c6ad3d6873a308a004882419, e4de8ca013f06ad4a0bf40420a291c23990e4131] stable/5.10: [7193ad3e50e596ac2192531c58ba83b9e6d2444b, e4de8ca013f06ad4a0bf40420a291c23990e4131] stable/5.15: [36dfdf11af49d3c009c711fb16f5c6e7a274505d, 6eea4ace62fa6414432692ee44f0c0a3d541d97a] stable/5.4: [fd6de5a0cd42fc43810bd74ad129d98ab962ec6b, 9978777c5409d6c856cac1adf5930e3c84f057be] * Updated CVEs no updated CVEs. Currently tracking CVEs CVE-2021-31615: Unencrypted Bluetooth Low Energy baseband links in Bluetooth Core Specifications 4.0 through 5.2 There is no fix information. CVE-2020-26555: BR/EDR pin code pairing broken No fix information CVE-2020-26556: kernel: malleable commitment Bluetooth Mesh Provisioning No fix information. CVE-2020-26557: kernel: predictable Authvalue in Bluetooth Mesh Provisioning Leads to MITM No fix information. CVE-2020-26559: kernel: Authvalue leak in Bluetooth Mesh Provisioning No fix information. CVE-2020-26560: kernel: impersonation attack in Bluetooth Mesh Provisioning No fix information. Regards, -- Masami Ichikawa Cybertrust Japan Co., Ltd. Email :masami.ichikawa@... :masami.ichikawa@...
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Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Nobuhiro Iwamatsu
Hi!
Hi All, LGTM. I can merge this seriese, If there is no objection. Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...> Best regards, Nobuhiro ________________________________________ 差出人: Lad Prabhakar <prabhakar.mahadev-lad.rj@...> 送信日時: 2021年12月15日 9:46 宛先: cip-dev@...; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek CC: Biju Das; Lad Prabhakar 件名: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK Hi All, This patch series adds initial support for Renesas RZ/G2L SoC [0] and Renesas RZ/G2L SMARC EVK [1]. The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec (H.264). It also has many interfaces such as camera input, display output, USB 2.0, and Gbit-Ether, making it ideal for applications such as entry-class industrial human-machine interfaces (HMIs) and embedded devices with video capabilities. Patches add support for the following: * Documentation for RZ/G2{L,LC,UL} SoC variants * Documentation for Renesas SMARC EVK * SYSC binding doc required for SoC identification * SoC identification support * Enabling ARCH_R9A07G044 in defconfig All the patches have been cherry picked from v5.16-rc5 [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ rz-arm-based-high-end-32-64-bit-mpus/rzg2l-general-purpose-microprocessors-dual- core-arm-cortex-a55-12-ghz-cpus-3d-graphics-and-video-codec [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit Cheers, Prabhakar Lad Prabhakar (7): dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants dt-bindings: arm: renesas: Document SMARC EVK dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's arm64: defconfig: Enable ARCH_R9A07G044 .../devicetree/bindings/arm/renesas.yaml | 18 ++++++ .../bindings/power/renesas,rzg2l-sysc.yaml | 63 +++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/soc/renesas/Kconfig | 5 ++ drivers/soc/renesas/renesas-soc.c | 33 +++++++++- 5 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml -- 2.17.1
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Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Nobuhiro Iwamatsu
Hi all,
I think I need to add the board to LAB first. Of course, source code reviews andI have reviewed patches and they look okay to me. I'll proceed withWe don't have any boards in the CIP labs yet, but there is a plan to add some. build tests are possible. And If my understand is correctoly, I think this is a new board that is not on the reference board list. I don't think this has been discussed at TSC. I think it needs to be on the agenda at TSC, whether it's a reference board for the 5.10-cip kernel. Best regards, Nobuhiro Best regards, Nobuhiro ________________________________________ 差出人: Chris Paterson <Chris.Paterson2@...> 送信日時: 2021年12月15日 19:34 宛先: cip-dev@...; Prabhakar Mahadev Lad CC: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek; Biju Das 件名: RE: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK Hello Pavel, From: cip-dev@... <cip-dev@...> OnWe don't have any boards in the CIP labs yet, but there is a plan to add some. Kind regards, Chris
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