Date   

cip-gitlab/ci/pavel/linux-test ltp-ipc: 7 runs, 1 regressions (v5.10.131-cip13) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/pavel/linux-test ltp-ipc: 7 runs, 1 regressions (v5.10.131-cip13)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
-----------------------------+--------+---------------+----------+------------------------------+------------
hp-x360-12b-c...4020-octopus | x86_64 | lab-collabora | gcc-10 | x86_64_defcon...6-chromebook | 1

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fpavel%2Flinux-test/kernel/v5.10.131-cip13/plan/ltp-ipc/

Test: ltp-ipc
Tree: cip-gitlab
Branch: ci/pavel/linux-test
Describe: v5.10.131-cip13
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: e217bcd84090afd29c7a9ab120fb3c8ff8844478

Test suite revisions:
ltp-tests
URL: https://github.com/linux-test-project/ltp.git
SHA: bda92ad659a52d38ac810099f69adff626b064c6


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
-----------------------------+--------+---------------+----------+------------------------------+------------
hp-x360-12b-c...4020-octopus | x86_64 | lab-collabora | gcc-10 | x86_64_defcon...6-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97d1ce4c9718ca0daf056

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: x86_64_defconfig+x86-chromebook
Compiler: gcc-10 (gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/lab-collabora/ltp-ipc-hp-x360-12b-ca0010nr-n4020-octopus.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/lab-collabora/ltp-ipc-hp-x360-12b-ca0010nr-n4020-octopus.html
Rootfs: http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20220716.0/amd64/initrd.cpio.gz


* ltp-ipc.login: https://kernelci.org/test/case/id/62e97d1ce4c9718ca0daf057
failing since 7 days (last pass: v5.10.129-cip12-36-g21d9d56f4de5a, first fail: v4.4-st5-586-geb97410e0086c)


[PATCH 4.4-cip] Revert "ASoC: rt5645: Fix errorenous cleanup order"

Jan Kiszka
 

From: Jan Kiszka <jan.kiszka@...>

This reverts commit 32ab6f27ac8264da14ff3b8dc17da1013fb5560f.

Misplaced in 4.4 because there is no btn_check_timer in this kernel.

Signed-off-by: Jan Kiszka <jan.kiszka@...>
---
sound/soc/codecs/rt5645.c | 6 ------
1 file changed, 6 deletions(-)

diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
index 15bc81ffcf45..b74840b5becf 100644
--- a/sound/soc/codecs/rt5645.c
+++ b/sound/soc/codecs/rt5645.c
@@ -3676,12 +3676,6 @@ static int rt5645_i2c_remove(struct i2c_client *i2c)
if (i2c->irq)
free_irq(i2c->irq, rt5645);

- /*
- * Since the rt5645_btn_check_callback() can queue jack_detect_work,
- * the timer need to be delted first
- */
- del_timer_sync(&rt5645->btn_check_timer);
-
cancel_delayed_work_sync(&rt5645->jack_detect_work);
cancel_delayed_work_sync(&rt5645->rcclock_work);

--
2.35.3


cip-gitlab/ci/pavel/linux-test baseline-nfs: 14 runs, 3 regressions (v5.10.131-cip13) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/pavel/linux-test baseline-nfs: 14 runs, 3 regressions (v5.10.131-cip13)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
-----------------+-------+---------------+----------+----------------------------+------------
rk3399-gru-kevin | arm64 | lab-collabora | gcc-10 | defconfig+arm64-chromebook | 3

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fpavel%2Flinux-test/kernel/v5.10.131-cip13/plan/baseline-nfs/

Test: baseline-nfs
Tree: cip-gitlab
Branch: ci/pavel/linux-test
Describe: v5.10.131-cip13
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: e217bcd84090afd29c7a9ab120fb3c8ff8844478


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
-----------------+-------+---------------+----------+----------------------------+------------
rk3399-gru-kevin | arm64 | lab-collabora | gcc-10 | defconfig+arm64-chromebook | 3

Details: https://kernelci.org/test/plan/id/62e97de3203c33deafdaf0dd

Results: 84 PASS, 4 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-collabora/baseline-nfs-rk3399-gru-kevin.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-collabora/baseline-nfs-rk3399-gru-kevin.html
Rootfs: http://storage.kernelci.org/images/rootfs/debian/bullseye/20220718.0/arm64/initrd.cpio.gz


* baseline-nfs.bootrr.cros-ec-sensors-gyro0-probed: https://kernelci.org/test/case/id/62e97de4203c33deafdaf120
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)

2022-08-02T19:41:04.916667 <8>[ 93.188208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-sensors-accel1-probed RESULT=fail>
2022-08-02T19:41:05.951876 /lava-6951001/1/../bin/lava-test-case
2022-08-02T19:41:05.983316 <8>[ 94.255469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-sensors-gyro0-probed RESULT=fail>

* baseline-nfs.bootrr.cros-ec-sensors-accel1-probed: https://kernelci.org/test/case/id/62e97de4203c33deafdaf121
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)

2022-08-02T19:41:04.885961 /lava-6951001/1/../bin/lava-test-case

* baseline-nfs.bootrr.cros-ec-sensors-accel0-probed: https://kernelci.org/test/case/id/62e97de4203c33deafdaf122
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)

2022-08-02T19:41:02.777507 <8>[ 91.049143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-sensors-driver-present RESULT=pass>
2022-08-02T19:41:03.811008 /lava-6951001/1/../bin/lava-test-case
2022-08-02T19:41:03.844478 <8>[ 92.116469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-sensors-accel0-probed RESULT=fail>


cip-gitlab/ci/pavel/linux-test baseline: 36 runs, 6 regressions (v5.10.131-cip13) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/pavel/linux-test baseline: 36 runs, 6 regressions (v5.10.131-cip13)

Regressions Summary
-------------------

platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv2-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv2-uefi | arm64 | lab-collabora | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
qemu_arm64-virt-gicv3-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1
zynqmp-zcu102 | arm64 | lab-cip | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/job/cip-gitlab/branch/ci%2Fpavel%2Flinux-test/kernel/v5.10.131-cip13/plan/baseline/

Test: baseline
Tree: cip-gitlab
Branch: ci/pavel/linux-test
Describe: v5.10.131-cip13
URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
SHA: e217bcd84090afd29c7a9ab120fb3c8ff8844478


Test Regressions
----------------


platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97e26da926de7b1daf08b

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e97e26da926de7b1daf08c
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97e118a38ddb6e4daf090

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv2-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e97e118a38ddb6e4daf091
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv2-uefi | arm64 | lab-collabora | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97de4328cb8cec9daf056

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-collabora/baseline-qemu_arm64-virt-gicv2-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-collabora/baseline-qemu_arm64-virt-gicv2-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e97de4328cb8cec9daf057
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3 | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97e4e5ffd4cb83bdaf069

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e97e4e5ffd4cb83bdaf06a
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
qemu_arm64-virt-gicv3-uefi | arm64 | lab-broonie | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97e3b5ffd4cb83bdaf056

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3-uefi.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-broonie/baseline-qemu_arm64-virt-gicv3-uefi.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e97e3b5ffd4cb83bdaf057
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)



platform | arch | lab | compiler | defconfig | regressions
---------------------------+-------+---------------+----------+----------------------------+------------
zynqmp-zcu102 | arm64 | lab-cip | gcc-10 | defconfig+arm64-chromebook | 1

Details: https://kernelci.org/test/plan/id/62e97dd0203c33deafdaf06d

Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig+arm64-chromebook
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-cip/baseline-zynqmp-zcu102.txt
HTML log: https://storage.kernelci.org//cip-gitlab/ci-pavel-linux-test/v5.10.131-cip13/arm64/defconfig+arm64-chromebook/gcc-10/lab-cip/baseline-zynqmp-zcu102.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20220718.0/arm64/rootfs.cpio.gz


* baseline.login: https://kernelci.org/test/case/id/62e97dd0203c33deafdaf06e
failing since 84 days (last pass: v4.19.233-516-ge5e741fbfc87, first fail: v5.10.109-cip5-384-g722204542e8a)


4.4.302-cip70: 'struct rt5645_priv' has no member named 'btn_check_timer'

Jan Kiszka
 

Hi Pavel,

we have a build-regression in 4.4.302-cip70:

../sound/soc/codecs/rt5645.c: In function 'rt5645_i2c_remove':
../sound/soc/codecs/rt5645.c:3683:24: error: 'struct rt5645_priv' has no member named 'btn_check_timer'
3683 | del_timer_sync(&rt5645->btn_check_timer);
| ^~
make[6]: *** [../scripts/Makefile.build:280: sound/soc/codecs/rt5645.o] Error 1

That's related to 32ab6f27ac8264da14ff3b8dc17da1013fb5560f, a commit
that either does not belong into 4.4 or is missing dependencies.

I guess this slipped through because the affectd driver is not in any of
our cip configs - but it is enabled in multi_v7_defconfig...

Jan

--
Siemens AG, Technology
Competence Center Embedded Linux


cip-gitlab/ci/pavel/linux-test build: 127 builds: 3 failed, 124 passed, 4 errors, 9 warnings (v5.10.131-cip13) #kernelci

kernelci.org bot <bot@...>
 

cip-gitlab/ci/pavel/linux-test build: 127 builds: 3 failed, 124 passed, 4 errors, 9 warnings (v5.10.131-cip13)

Full Build Summary: https://kernelci.org/build/cip-gitlab/branch/ci%2Fpavel%2Flinux-test/kernel/v5.10.131-cip13/

Tree: cip-gitlab
Branch: ci/pavel/linux-test
Git Describe: v5.10.131-cip13
Git Commit: e217bcd84090afd29c7a9ab120fb3c8ff8844478
Git URL: https://gitlab.com/cip-project/cip-kernel/linux-cip.git
Built: 7 unique architectures

Build Failures Detected:

arm:
rpc_defconfig: (gcc-10) FAIL

mips:
ip27_defconfig: (gcc-10) FAIL
ip28_defconfig: (gcc-10) FAIL

Errors and Warnings Detected:

arc:

arm64:

arm:
rpc_defconfig (gcc-10): 4 errors

i386:

mips:
32r2el_defconfig (gcc-10): 1 warning
decstation_defconfig (gcc-10): 1 warning
decstation_r4k_defconfig (gcc-10): 1 warning
lemote2f_defconfig (gcc-10): 1 warning
rm200_defconfig (gcc-10): 1 warning

riscv:
rv32_defconfig (gcc-10): 4 warnings

x86_64:

Errors summary:

2 arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3m
2 arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’

Warnings summary:

2 kernel/rcu/tasks.h:710:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function]
2 <stdin>:830:2: warning: #warning syscall fstat64 not implemented [-Wcpp]
2 <stdin>:1127:2: warning: #warning syscall fstatat64 not implemented [-Wcpp]
1 net/mac80211/mlme.c:4349:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=]
1 drivers/block/paride/bpck.c:32: warning: "PC" redefined
1 WARNING: modpost: Symbol info of vmlinux is missing. Unresolved symbol check will be entirely skipped.

Section mismatches summary:

1 WARNING: modpost: vmlinux.o(___ksymtab_gpl+ixp4xx_irq_init+0x0): Section mismatch in reference from the variable __ksymtab_ixp4xx_irq_init to the function .init.text:ixp4xx_irq_init()
1 WARNING: modpost: vmlinux.o(___ksymtab+prom_init_numa_memory+0x0): Section mismatch in reference from the variable __ksymtab_prom_init_numa_memory to the function .init.text:prom_init_numa_memory()

================================================================================

Detailed per-defconfig build reports:

--------------------------------------------------------------------------------
32r2el_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches

Warnings:
WARNING: modpost: Symbol info of vmlinux is missing. Unresolved symbol check will be entirely skipped.

--------------------------------------------------------------------------------
allnoconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
allnoconfig (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
allnoconfig (i386, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
am200epdkit_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ar7_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
aspeed_g5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
at91_dt_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ath25_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
bcm2835_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
bcm47xx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
bcm63xx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
bigsur_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
bmips_be_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
bmips_stb_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
capcella_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
cavium_octeon_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ci20_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
cm_x300_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
cobalt_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
colibri_pxa270_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
corgi_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
cu1000-neo_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
cu1830-neo_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
decstation_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches

Warnings:
kernel/rcu/tasks.h:710:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function]

--------------------------------------------------------------------------------
decstation_r4k_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches

Warnings:
kernel/rcu/tasks.h:710:13: warning: ‘show_rcu_tasks_rude_gp_kthread’ defined but not used [-Wunused-function]

--------------------------------------------------------------------------------
defconfig (riscv, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
defconfig+arm64-chromebook (arm64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
dove_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
e55_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ep93xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
eseries_pxa_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
exynos_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ezx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
footbridge_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
fuloong2e_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
gemini_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
gpr_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
h3600_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
h5000_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
hisi_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
hsdk_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
i386_defconfig (i386, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
imote2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
imx_v4_v5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ip27_defconfig (mips, gcc-10) — FAIL, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ip28_defconfig (mips, gcc-10) — FAIL, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ip32_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
ixp4xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

Section mismatches:
WARNING: modpost: vmlinux.o(___ksymtab_gpl+ixp4xx_irq_init+0x0): Section mismatch in reference from the variable __ksymtab_ixp4xx_irq_init to the function .init.text:ixp4xx_irq_init()

--------------------------------------------------------------------------------
jmr3927_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
jornada720_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
keystone_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
lemote2f_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches

Warnings:
net/mac80211/mlme.c:4349:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=]

--------------------------------------------------------------------------------
loongson1b_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
loongson1c_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
loongson3_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

Section mismatches:
WARNING: modpost: vmlinux.o(___ksymtab+prom_init_numa_memory+0x0): Section mismatch in reference from the variable __ksymtab_prom_init_numa_memory to the function .init.text:prom_init_numa_memory()

--------------------------------------------------------------------------------
lpc32xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mainstone_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
malta_kvm_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
malta_kvm_guest_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
malta_qemu_32r6_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
maltaaprp_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
maltasmvp_eva_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
maltaup_xpa_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
milbeaut_m10v_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mini2440_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mmp2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mpc30x_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mps2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
multi_v4t_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
multi_v5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mvebu_v5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
mvebu_v7_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
neponset_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
netwinder_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
nlm_xlp_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
nommu_k210_defconfig (riscv, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
nsimosci_hs_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
nsimosci_hs_smp_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
omap1_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
omap2plus_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
pcm027_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
pic32mzda_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
pistachio_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
prima2_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
pxa168_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
pxa910_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
qcom_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
qi_lb60_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
rbtx49xx_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
rm200_defconfig (mips, gcc-10) — PASS, 0 errors, 1 warning, 0 section mismatches

Warnings:
drivers/block/paride/bpck.c:32: warning: "PC" redefined

--------------------------------------------------------------------------------
rpc_defconfig (arm, gcc-10) — FAIL, 4 errors, 0 warnings, 0 section mismatches

Errors:
arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3m
arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’
arm-linux-gnueabihf-gcc: error: unrecognized -march target: armv3m
arm-linux-gnueabihf-gcc: error: missing argument to ‘-march=’

--------------------------------------------------------------------------------
rs90_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
rv32_defconfig (riscv, gcc-10) — PASS, 0 errors, 4 warnings, 0 section mismatches

Warnings:
<stdin>:830:2: warning: #warning syscall fstat64 not implemented [-Wcpp]
<stdin>:1127:2: warning: #warning syscall fstatat64 not implemented [-Wcpp]
<stdin>:830:2: warning: #warning syscall fstat64 not implemented [-Wcpp]
<stdin>:1127:2: warning: #warning syscall fstatat64 not implemented [-Wcpp]

--------------------------------------------------------------------------------
s3c6400_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
s5pv210_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
sama5_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
sb1250_swarm_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
shmobile_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
simpad_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
spear13xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
spear3xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
spear6xx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
spitz_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
stm32_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
sunxi_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tango4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tb0219_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tb0226_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tb0287_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tct_hammer_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tegra_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tinyconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
tinyconfig (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
trizeps4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
u300_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
u8500_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
vdk_hs38_smp_defconfig (arc, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
versatile_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
vf610m4_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
vt8500_v6_v7_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
workpad_defconfig (mips, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
x86_64_defconfig (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
x86_64_defconfig+x86-chromebook (x86_64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
xcep_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
zeus_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

--------------------------------------------------------------------------------
zx_defconfig (arm, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches

---
For more info write to <info@...>


Re: [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support

Pavel Machek
 

Hi!

This patch series aims to add Basic board support for SMARC EVK
based on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same
SMARC EVK board, but SoM is different and pin mapping of SoM
module is different.

All these patches are cherry-picked from the mainline.
Series looks okay to me. I can apply it if there are no other commands
(and if it passes testing).

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC

Pavel Machek
 

Hi!

commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream.

The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.

Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take
care of the DRP-AI clocks/resets.
Ok, so this reuse is quite interesting.


+++ b/drivers/clk/renesas/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
+obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
They share the same source file, but the file will be different basen
on config options.

If you enable CONFIG_CLK_R9A07G044, you get g044 support but not g054
support.

If you enable CONFIG_CLK_R9A07G054, you get both g044 and g054
support, you can't disable g044.

This is quite strange, but probably not a problem. For symmetry, I'd
not mind conditional compilation of g044 parts; or perhaps even better
get rid of condtional compilation of g045 parts -- I don't believe
space savings are significant.

Best regards,
Pavel


index 46359afef0d4..bdfabb992a20 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
+
+#ifdef CONFIG_CLK_R9A07G054
+const struct rzg2l_cpg_info r9a07g054_cpg_info = {
+ /* Core Clocks */
+ .core_clks = core_clks.common,
+ .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r9a07g044_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
+
+ /* Module Clocks */
+ .mod_clks = mod_clks.common,
+ .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
+ .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
+
+ /* Resets */
+ .resets = r9a07g044_resets,
+ .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
};
+#endif
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index edd0abe34a37..486d0656c58a 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
.compatible = "renesas,r9a07g044-cpg",
.data = &r9a07g044_cpg_info,
},
+#endif
+#ifdef CONFIG_CLK_R9A07G054
+ {
+ .compatible = "renesas,r9a07g054-cpg",
+ .data = &r9a07g054_cpg_info,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 5729d102034b..ce657beaf160 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -203,5 +203,6 @@ struct rzg2l_cpg_info {
};

extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
+extern const struct rzg2l_cpg_info r9a07g054_cpg_info;

#endif
--
2.25.1
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK

Pavel Machek
 

Hi!

Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.

Signed-off-by: Biju Das <biju.das.jz@...>
Git is a bit unhappy with blank lines --

Applying: arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
.git/rebase-apply/patch:171: new blank line at EOF.
+
.git/rebase-apply/patch:253: new blank line at EOF.
+

-- but as before that is probably not worth solving in separate patch.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [isar-cip-core][RFC 0/2] clean up kas/opt

Jan Kiszka
 

On 02.08.22 11:15, Jan Kiszka wrote:
On 01.08.22 16:57, Quirin Gylstorff wrote:
From: Quirin Gylstorff <quirin.gylstorff@...>

Remove the kas option for efibootguard as it cannot build a image.
Move the package installation for swupdate to the include.

Quirin Gylstorff (2):
kas: Remove efibootguard.yml
kas/opt/swupdate: Move the package installation to swupdate.inc

kas/opt/ebg-secure-boot-snakeoil.yml | 10 +++----
kas/opt/ebg-swu.yml | 9 +++----
kas/opt/efibootguard.yml | 39 ----------------------------
kas/opt/swupdate.yml | 4 ---
recipes-core/images/efibootguard.inc | 26 +++++++++++++++++++
recipes-core/images/swupdate.inc | 3 +++
6 files changed, 36 insertions(+), 55 deletions(-)
delete mode 100644 kas/opt/efibootguard.yml
create mode 100644 recipes-core/images/efibootguard.inc
Thanks, applied.
This breaks something when building kas-cip.yml:kas/board/qemu-arm64.yml:kas/opt/5.10.yml:kas/opt/bullseye.yml:kas/opt/ebg-secure-boot-snakeoil.yml:

NOTE: Executing Tasks
ERROR: cip-core-image-1.0-r0 do_image_wic: ExecutionError('/build/tmp/work/cip-core-bullseye-arm64/cip-core-image-qemu-arm64/1.0-r0/temp/run.do_image_wic.24213', 1, None, None)
ERROR: Logfile of failure stored in: /build/tmp/work/cip-core-bullseye-arm64/cip-core-image-qemu-arm64/1.0-r0/temp/log.do_image_wic.24213
Log data follows:
| DEBUG: Executing python function set_image_size
| DEBUG: Python function set_image_size finished
| DEBUG: Executing shell function do_image_wic
| INFO: Creating image(s)...
|
| WARNING: KERNEL_IMAGE not set. Use default:
| WARNING: INITRD_IMAGE not set
|
| ERROR: _exec_cmd: bg_gen_unified_kernel /build/tmp/work/cip-core-bullseye-arm64/cip-core-image-qemu-arm64/1.0-r0/rootfs/usr/share/efibootguard/kernel-stubaa64.efi /build/tmp/deploy/images/qemu-arm64/vmlinuz /build/tmp/deploy/images/qemu-arm64/linux.efi -c "panic=5" -i /build/tmp/deploy/images/qemu-arm64/initrd.img returned '2' instead of 0
| output: usage: bg_gen_unified_kernel [-h] [-c "CMDLINE"] [-d DTB] [-i INITRD]
| STUB KERNEL UNIFIEDIMAGE
| bg_gen_unified_kernel: error: argument KERNEL: can't open '/build/tmp/deploy/images/qemu-arm64/vmlinuz': [Errno 2] No such file or directory: '/build/tmp/deploy/images/qemu-arm64/vmlinuz'
|
| WARNING: exit code 1 from a shell command.
| ERROR: ExecutionError('/build/tmp/work/cip-core-bullseye-arm64/cip-core-image-qemu-arm64/1.0-r0/temp/run.do_image_wic.24213', 1, None, None)
ERROR: Task (/repo/recipes-core/images/cip-core-image.bb:do_image_wic) failed with exit code '1'
NOTE: Tasks Summary: Attempted 160 tasks of which 139 didn't need to be rerun and 1 failed.

I'm pulling the series from next again (wasn't pushed yet, noticed locally).

Jan

--
Siemens AG, Technology
Competence Center Embedded Linux


[PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board

Biju Das
 

commit fa00d6dc19283bee13f0390546f741293f6d2d9a upstream.

SCIF1 interface is available on PMOD1 connector (CN7) on carrier board.

This patch adds pinmux and scif1 node to carrier board dtsi file for
RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 26 +++++++++++++++++++
2 files changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 1032f6563515..ec9e08ec0822 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -17,6 +17,13 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};

+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
+ };
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index ca5ca7ce6692..1b59ef376296 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -34,3 +34,29 @@
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
+
+/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/ {
+ aliases {
+ serial1 = &scif1;
+ };
+};
+
+/*
+ * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
+ * SW1 should be at position 2->3 so that SER0_CTS# line is activated
+ * SW2 should be at position 2->3 so that SER0_TX line is activated
+ * SW3 should be at position 2->3 so that SER0_RX line is activated
+ * SW4 should be at position 2->3 so that SER0_RTS# line is activated
+ */
+#if (!SW_SCIF_CAN && PMOD1_SER0)
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+#endif
--
2.25.1


[PATCH 5.10.y-cip 23/24] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings

Biju Das
 

commit 2ed3b5d9540b246d7a1ec98971914ee810b40086 upstream.

RZ/G2LC SoM uses DIP-SWitch SW1 for various pin multiplexing functions.

This patch describes DIP-SWitch SW1 settings on SoM and adds the
corresponding macros for enabling pinmux functionality on RZ/G2LC
SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220203170636.7747-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 4 +--
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 36 +++++++++++++++++++
2 files changed, 37 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index af84fd6c8a81..50abdabc374a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -7,9 +7,7 @@

/dts-v1/;
#include "r9a07g044c2.dtsi"
-#include "rzg2lc-smarc-som.dtsi"
-#include "rzg2lc-smarc-pinfunction.dtsi"
-#include "rz-smarc-common.dtsi"
+#include "rzg2lc-smarc.dtsi"

/ {
model = "Renesas SMARC EVK based on r9a07g044c2";
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
new file mode 100644
index 000000000000..ca5ca7ce6692
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC EVK parts
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/*
+ * DIP-Switch SW1 setting on SoM
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
+ * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
+ * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
+ * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
+ * Please change below macros according to SW1 setting
+ */
+
+#define SW_SCIF_CAN 0
+#if (SW_SCIF_CAN)
+/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
+#define SW_RSPI_CAN 0
+#else
+/* Please set SW_RSPI_CAN. Default value is 1 */
+#define SW_RSPI_CAN 1
+#endif
+
+#if (SW_SCIF_CAN & SW_RSPI_CAN)
+#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
+#endif
+
+#include "rzg2lc-smarc-som.dtsi"
+#include "rzg2lc-smarc-pinfunction.dtsi"
+#include "rz-smarc-common.dtsi"
--
2.25.1


[PATCH 5.10.y-cip 22/24] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file

Biju Das
 

commit 726fd781195dc99cdcb60b2678694bfa5ccd1825 upstream.

RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is
different.

Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK
uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available
on PMOD1.

This patch adds support for handling the pin mapping differences by moving
definitions common to RZ/G2L and RZ/G2LC to a common dtsi file.

Signed-off-by: Biju Das <biju.das.jz@...>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220203170636.7747-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 9 +-
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 1 +
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 1 +
.../boot/dts/renesas/rz-smarc-common.dtsi | 207 ++++++++++++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 193 ----------------
5 files changed, 210 insertions(+), 201 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 8d671111d973..af84fd6c8a81 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -9,12 +9,11 @@
#include "r9a07g044c2.dtsi"
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
-#include "rzg2l-smarc.dtsi"
+#include "rz-smarc-common.dtsi"

/ {
model = "Renesas SMARC EVK based on r9a07g044c2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
-
};

&canfd {
@@ -75,12 +74,6 @@ &phyrst {
status = "disabled";
};

-&scif2 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index 886d38886d05..bc2af6c92ccd 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -9,6 +9,7 @@
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rz-smarc-common.dtsi"
#include "rzg2l-smarc.dtsi"

/ {
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
index 39ef55bfe0c3..49d141db53f7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
@@ -9,6 +9,7 @@
#include "r9a07g054l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rz-smarc-common.dtsi"
#include "rzg2l-smarc.dtsi"

/ {
diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
new file mode 100644
index 000000000000..588117aafaca
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/*
+ * SSI-WM8978
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer cset name='Left Input Mixer L2 Switch' on
+ * amixer cset name='Right Input Mixer R2 Switch' on
+ * amixer cset name='Headphone Playback Volume' 100
+ * amixer cset name='PCM Volume' 100%
+ * amixer cset name='Input PGA Volume' 25
+ *
+ */
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c3 = &i2c3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ audio_mclock: audio_mclock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ snd_rzg2l: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&cpu_dai>;
+ simple-audio-card,frame-master = <&cpu_dai>;
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,widgets = "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "L2", "Mic Bias",
+ "R2", "Mic Bias",
+ "Mic Bias", "Microphone Jack";
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&ssi0>;
+ };
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&audio_mclock>;
+ sound-dai = <&wm8978>;
+ };
+ };
+
+ usb0_vbus_otg: regulator-usb0-vbus-otg {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB0_VBUS_OTG";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+};
+
+&audio_clk1{
+ clock-frequency = <11289600>;
+};
+
+&audio_clk2{
+ clock-frequency = <12288000>;
+};
+
+&canfd {
+ pinctrl-0 = <&can0_pins &can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&ssi0 {
+ pinctrl-0 = <&ssi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 78034f36156d..33ddfd18bd56 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -8,164 +8,13 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

-/*
- * SSI-WM8978
- *
- * This command is required when Playback/Capture
- *
- * amixer cset name='Left Input Mixer L2 Switch' on
- * amixer cset name='Right Input Mixer R2 Switch' on
- * amixer cset name='Headphone Playback Volume' 100
- * amixer cset name='PCM Volume' 100%
- * amixer cset name='Input PGA Volume' 25
- *
- */
-
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1

/ {
aliases {
- serial0 = &scif0;
serial1 = &scif2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c3 = &i2c3;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- audio_mclock: audio_mclock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
- snd_rzg2l: sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&cpu_dai>;
- simple-audio-card,frame-master = <&cpu_dai>;
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,widgets = "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "L2", "Mic Bias",
- "R2", "Mic Bias",
- "Mic Bias", "Microphone Jack";
-
- cpu_dai: simple-audio-card,cpu {
- sound-dai = <&ssi0>;
- };
-
- codec_dai: simple-audio-card,codec {
- clocks = <&audio_mclock>;
- sound-dai = <&wm8978>;
- };
- };
-
- usb0_vbus_otg: regulator-usb0-vbus-otg {
- compatible = "regulator-fixed";
-
- regulator-name = "USB0_VBUS_OTG";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vccq_sdhi1: regulator-vccq-sdhi1 {
- compatible = "regulator-gpio";
- regulator-name = "SDHI1 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
- gpios-states = <1>;
- states = <3300000 1>, <1800000 0>;
- };
-};
-
-&audio_clk1{
- clock-frequency = <11289600>;
-};
-
-&audio_clk2{
- clock-frequency = <12288000>;
-};
-
-&canfd {
- pinctrl-0 = <&can0_pins &can1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
};
-
- channel1 {
- status = "okay";
- };
-};
-
-&ehci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&hsusb {
- dr_mode = "otg";
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
-
- status = "okay";
-
- wm8978: codec@1a {
- compatible = "wlf,wm8978";
- #sound-dai-cells = <0>;
- reg = <0x1a>;
- };
-};
-
-&ohci0 {
- dr_mode = "otg";
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&phyrst {
- status = "okay";
-};
-
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
- pinctrl-names = "default";
- status = "okay";
};

/*
@@ -184,45 +33,3 @@ &scif2 {
status = "okay";
};
#endif
-
-&sdhi1 {
- pinctrl-0 = <&sdhi1_pins>;
- pinctrl-1 = <&sdhi1_pins_uhs>;
- pinctrl-names = "default", "state_uhs";
-
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&vccq_sdhi1>;
- bus-width = <4>;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-0 = <&spi1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&ssi0 {
- pinctrl-0 = <&ssi0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-
- vbus-supply = <&usb0_vbus_otg>;
- status = "okay";
-};
-
-&usb2_phy1 {
- pinctrl-0 = <&usb1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
--
2.25.1


[PATCH 5.10.y-cip 21/24] arm64: defconfig: Enable ARCH_R9A07G054

Biju Das
 

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>

commit ca9df4a75a208f3294a9a09b84ffa1bc89d3e0df upstream.

Enable support for the Renesas RZ/V2L SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Reviewed-by: Biju Das <biju.das.jz@...>
Link: https://lore.kernel.org/r/20220308140033.10501-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 58a79a3e1cd0..7975a4b6a84a 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -963,6 +963,7 @@ CONFIG_ARCH_R8A77980=y
CONFIG_ARCH_R8A77990=y
CONFIG_ARCH_R8A77995=y
CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A07G054=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ARCH_TEGRA_132_SOC=y
CONFIG_ARCH_TEGRA_210_SOC=y
--
2.25.1


[PATCH 5.10.y-cip 20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK

Biju Das
 

commit f91c4c74796acca0a5a3bde747948a844eb2c30b upstream.

Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2):
- memory
- External input clock
- CPG
- Pin controller
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L with the same pin mapping.
Delete the gpio-hog nodes from pinctrl as they will be added later when
the functionality has been tested.

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220110134659.30424-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/Makefile | 2 ++
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 25 +++++++++++++++++++
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +-
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +-
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 2 +-
5 files changed, 30 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 962a66332236..8815c5eb4cfc 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -59,3 +59,5 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb

dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
+
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
new file mode 100644
index 000000000000..39ef55bfe0c3
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054l2.dtsi"
+#include "rzg2l-smarc-som.dtsi"
+#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g054l2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
+};
+
+&pinctrl {
+ /delete-node/ can0-stb;
+ /delete-node/ can1-stb;
+ /delete-node/ gpio-sd0-pwr-en-hog;
+ /delete-node/ sd0-dev-sel-hog;
+ /delete-node/ sd1-pwr-en-hog;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 71d83e447670..2ef217445f72 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2L SMARC pincontrol parts
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 41fdae7ba66b..879375c0395e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2L SMARC SOM common parts
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 46abb29718cc..78034f36156d 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2L SMARC EVK common parts
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
--
2.25.1


[PATCH 5.10.y-cip 19/24] arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC

Biju Das
 

commit 7c2b8198f4f321df03e285a931fab2a33668c88d upstream.

The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only
difference being that the RZ/V2L SoC has additional DRP-AI IP (AI
accelerator).

Add initial DTSI for the RZ/V2L SoC with below SoC specific dtsi files
for supporting single core and dual core devices:

r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts
r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts

Both the RZ/G2L and RZ/V2L SMARC EVK SoMs are identical apart from the
SoCs used, hence the common dtsi files (rzg2l-smarc*.dtsi) are shared
between the RZ/G2L and RZ/V2L SMARC EVKs. Place holders are added in
device nodes to avoid compilation errors for devices which have not been
enabled yet on the RZ/V2L SoC.

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220110134659.30424-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 +
arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 +
3 files changed, 529 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
new file mode 100644
index 000000000000..5d39e765c291
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2L SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g054-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g054";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_clk1: audio_clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio_clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ssi0: ssi@10049c00 {
+ reg = <0 0x10049c00 0 0x400>;
+ #sound-dai-cells = <0>;
+ /* place holder */
+ };
+
+ spi1: spi@1004b000 {
+ reg = <0 0x1004b000 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ sci0: serial@1004d000 {
+ compatible = "renesas,r9a07g054-sci", "renesas,sci";
+ reg = <0 0x1004d000 0 0x400>;
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCI0_RST>;
+ status = "disabled";
+ };
+
+ sci1: serial@1004d400 {
+ compatible = "renesas,r9a07g054-sci", "renesas,sci";
+ reg = <0 0x1004d400 0 0x400>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCI1_RST>;
+ status = "disabled";
+ };
+
+ canfd: can@10050000 {
+ reg = <0 0x10050000 0 0x8000>;
+ /* place holder */
+ };
+
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058000 0 0x400>;
+ /* place holder */
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058400 0 0x400>;
+ /* place holder */
+ };
+
+ i2c3: i2c@10058c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058c00 0 0x400>;
+ /* place holder */
+ };
+
+ adc: adc@10059000 {
+ reg = <0 0x10059000 0 0x400>;
+ /* place holder */
+ };
+
+ sbc: spi@10060000 {
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g054-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g054-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g054-pinctrl",
+ "renesas,r9a07g044-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 392>;
+ clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_GPIO_RSTN>,
+ <&cpg R9A07G054_GPIO_PORT_RESETN>,
+ <&cpg R9A07G054_GPIO_SPARE_RESETN>;
+ };
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g054-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_DMAC_ARESETN>,
+ <&cpg R9A07G054_DMAC_RST_ASYNC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ gpu: gpu@11840000 {
+ reg = <0x0 0x11840000 0x0 0x10000>;
+ /* place holder */
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sdhi0: mmc@11c00000 {
+ reg = <0x0 0x11c00000 0 0x10000>;
+ /* place holder */
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+ /* place holder */
+ };
+
+ eth0: ethernet@11c20000 {
+ compatible = "renesas,r9a07g054-gbeth",
+ "renesas,rzg2l-gbeth";
+ reg = <0 0x11c20000 0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
+ <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
+ <&cpg CPG_CORE R9A07G054_CLK_HP>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ eth1: ethernet@11c30000 {
+ compatible = "renesas,r9a07g054-gbeth",
+ "renesas,rzg2l-gbeth";
+ reg = <0 0x11c30000 0 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
+ <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
+ <&cpg CPG_CORE R9A07G054_CLK_HP>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ reg = <0 0x11c40000 0 0x10000>;
+ /* place holder */
+ };
+
+ ohci0: usb@11c50000 {
+ reg = <0 0x11c50000 0 0x100>;
+ /* place holder */
+ };
+
+ ohci1: usb@11c70000 {
+ reg = <0 0x11c70000 0 0x100>;
+ /* place holder */
+ };
+
+ ehci0: usb@11c50100 {
+ reg = <0 0x11c50100 0 0x100>;
+ /* place holder */
+ };
+
+ ehci1: usb@11c70100 {
+ reg = <0 0x11c70100 0 0x100>;
+ /* place holder */
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ reg = <0 0x11c50200 0 0x700>;
+ /* place holder */
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ reg = <0 0x11c70200 0 0x700>;
+ /* place holder */
+ };
+
+ hsusb: usb@11c60000 {
+ reg = <0 0x11c60000 0 0x10000>;
+ /* place holder */
+ };
+
+ wdt0: watchdog@12800800 {
+ reg = <0 0x12800800 0 0x400>;
+ /* place holder */
+ };
+
+ wdt1: watchdog@12800c00 {
+ reg = <0 0x12800C00 0 0x400>;
+ /* place holder */
+ };
+
+ wdt2: watchdog@12800400 {
+ reg = <0 0x12800400 0 0x400>;
+ /* place holder */
+ };
+
+ ostm0: timer@12801000 {
+ reg = <0x0 0x12801000 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm1: timer@12801400 {
+ reg = <0x0 0x12801400 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm2: timer@12801800 {
+ reg = <0x0 0x12801800 0x0 0x400>;
+ /* place holder */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
new file mode 100644
index 000000000000..c448cc6634c1
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g054l1", "renesas,r9a07g054";
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ };
+
+ timer {
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
new file mode 100644
index 000000000000..4d5914bc95d3
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g054l2", "renesas,r9a07g054";
+};
--
2.25.1


[PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC

Biju Das
 

commit 654f89f9496db716c4e9a79c3c6193d57cfaa963 upstream.

Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet
Interface is identical to one found on the RZ/G2L SoC. No driver changes
are required as generic compatible string "renesas,rzg2l-gbeth" will be
used as a fallback.

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Acked-by: Rob Herring <robh@...>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: David S. Miller <davem@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index 5237949cfabe..80197259afa8 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -45,7 +45,8 @@ properties:
- items:
- enum:
- renesas,r9a07g044-gbeth # RZ/G2{L,LC}
- - const: renesas,rzg2l-gbeth # RZ/G2L
+ - renesas,r9a07g054-gbeth # RZ/V2L
+ - const: renesas,rzg2l-gbeth # RZ/{G2L,V2L} family

reg: true

--
2.25.1


[PATCH 5.10.y-cip 17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register()

Biju Das
 

commit 2e08ab0427fe3e33a92a37cfe3b6db340ab7397f upstream.

Update rzg2l_gpio_register() to use driver data for chip->names
and check for gpio-range. This allows reusing the driver for
SoC's with different port pin definitions(eg:- RZ/G2UL SoC has
fewer ports compared to RZ/G2L and port pin definitions are
different).

Signed-off-by: Biju Das <biju.das.jz@...>
Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index ccee9c9e2e22..cb805502fb0f 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1090,12 +1090,12 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
}

if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
- of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) {
+ of_args.args[2] != pctrl->data->n_port_pins) {
dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
return -EINVAL;
}

- chip->names = rzg2l_gpio_names;
+ chip->names = pctrl->data->port_pins;
chip->request = rzg2l_gpio_request;
chip->free = rzg2l_gpio_free;
chip->get_direction = rzg2l_gpio_get_direction;
--
2.25.1


[PATCH 5.10.y-cip 16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled

Biju Das
 

commit 0c8fce49f24e7c8ee2bdff4761f414ad59bfa29a upstream.

RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin control support.

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
drivers/pinctrl/renesas/Kconfig | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 356a70739689..623d0c01e259 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -37,6 +37,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_RZG2L if ARCH_R9A07G044
+ select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -173,14 +174,15 @@ config PINCTRL_RZA2
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.

config PINCTRL_RZG2L
- bool "pin control support for RZ/G2L" if COMPILE_TEST
+ bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST
depends on OF
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
- This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
+ This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}
+ platforms.

config PINCTRL_PFC_R8A77470
bool "pin control support for RZ/G1C" if COMPILE_TEST
--
2.25.1


[PATCH 5.10.y-cip 15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl

Biju Das
 

commit c07b19de2f7ac91662aa99767815a258da6ef16f upstream.

Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package-
and pin-compatible with RZ/G2L. No driver changes are required as the
RZ/G2L compatible string "renesas,r9a07g044-pinctrl" will be used as a
fallback.

Signed-off-by: Biju Das <biju.das.jz@...>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...>
Acked-by: Rob Herring <robh@...>
Link: https://lore.kernel.org/r/20220110134659.30424-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@...>
Signed-off-by: Biju Das <biju.das.jz@...>
---
.../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 83488cd8673d..e4849a3680e0 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller

maintainers:
- Geert Uytterhoeven <geert+renesas@...>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@...>

description:
- The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+ The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
@@ -20,8 +20,15 @@ description:

properties:
compatible:
- enum:
- - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+
+ - items:
+ - enum:
+ - renesas,r9a07g054-pinctrl # RZ/V2L
+ - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L

reg:
maxItems: 1
--
2.25.1

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