Date   

[PATCH 5.10.y-cip 02/21] dt-bindings: usb: generic-ohci: Document dr_mode property

Lad Prabhakar
 

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 0c29ec921059abf110434addd8b8ed9032e710c7 upstream.

Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.

It fixes the dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210630073013.22415-2-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index 2178bcc401bc..05e1db57c312 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -79,6 +79,11 @@ properties:
iommus:
maxItems: 1

+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1


[PATCH 5.10.y-cip 01/21] dt-bindings: usb: generic-ehci: Document dr_mode property

Lad Prabhakar
 

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 31f21e2a09a150972f9188c3a785998131e843ba upstream.

Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.

It fixes dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210630073013.22415-3-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 247ef00381ea..78b235fb76df 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -91,6 +91,11 @@ properties:
iommus:
maxItems: 1

+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1


[PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD

Lad Prabhakar
 

Hi All,

This patch series adds USB and CANFD support to Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose),
which can later be merged once this patches have been merged.

[0] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/merge_requests/54

Cheers,
Prabhakar

Biju Das (12):
dt-bindings: usb: generic-ehci: Document dr_mode property
dt-bindings: usb: generic-ohci: Document dr_mode property
dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
reset: renesas: Add RZ/G2L usbphy control driver
dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/G2L
clk: renesas: r9a07g044: Add USB clocks/resets
arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
arm64: dts: renesas: r9a07g044: Add USB2.0 device support
arm64: dts: renesas: rzg2l-smarc: Enable USB2.0 support
arm64: defconfig: Enable RZ/G2L USBPHY control driver

Chunfeng Yun (1):
phy: renesas: convert to devm_platform_ioremap_resource

Geert Uytterhoeven (2):
dt-bindings: can: rcar_canfd: Group tuples in pin control properties
dt-bindings: can: rcar_canfd: Convert to json-schema

Lad Prabhakar (6):
can: rcar_canfd: Add support for RZ/G2L family
can: rcar_canfd: rcar_canfd_handle_channel_tx(): fix redundant
assignment
dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
clk: renesas: r9a07g044: Add clock and reset entries for CANFD
arm64: dts: renesas: r9a07g044: Add CANFD node

.../bindings/net/can/rcar_canfd.txt | 107 ------
.../bindings/net/can/renesas,rcar-canfd.yaml | 122 +++++++
.../bindings/phy/renesas,usb2-phy.yaml | 15 +
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 ++++
.../devicetree/bindings/usb/generic-ehci.yaml | 5 +
.../devicetree/bindings/usb/generic-ohci.yaml | 5 +
.../bindings/usb/renesas,usbhs.yaml | 26 +-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 155 ++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 61 ++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 19 +-
drivers/net/can/rcar/rcar_canfd.c | 338 ++++++++++++++----
drivers/phy/renesas/phy-rcar-gen2.c | 4 +-
drivers/phy/renesas/phy-rcar-gen3-pcie.c | 4 +-
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 101 ++++--
drivers/phy/renesas/phy-rcar-gen3-usb3.c | 4 +-
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 175 +++++++++
include/dt-bindings/clock/r9a07g044-cpg.h | 1 +
20 files changed, 997 insertions(+), 219 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
create mode 100644 Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml
create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
create mode 100644 drivers/reset/reset-rzg2l-usbphy-ctrl.c

--
2.17.1


Re: [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl

Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 22 December 2021 09:46
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L
pinctrl

Hi!

commit 7958f88aa6636f1927513c887a00e83168f12e35 upstream.

Add device tree binding documentation and header file for Renesas
RZ/G2L pinctrl.

+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+ power-source:
+ enum: [ 1800, 2500, 3300 ]
These are likely milliamps and millivolts, right? Elsewhere in device trees microvolts and microamps
are used, so that is not too consistent.
Its in millivolts in our case.

Is the unit mentioned somewhere / should it be?
I can update the renesas,rzg2l-pinctrl.yaml binding do to add a description and state the values are in millivolts.

Cheers,
Prabhakar


Re: [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver

Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 22 December 2021 09:48
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver

Hi!

Add support for pin and gpio controller driver for RZ/G2L SoC.

Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>.
+static int rzg2l_map_add_config(struct pinctrl_map *map,
+ const char *group_or_pin,
+ enum pinctrl_map_type type,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ unsigned long *cfgs;
+
+ cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
+ GFP_KERNEL);
Should we check for overflows here, too?
num_configs should take care while accessing the cfg.

Cheers,
Prabhakar


Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static

Lad Prabhakar
 

Hi Pavel,

Thank you for the review.

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 22 December 2021 10:05
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static

Hi!

commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream.

Don't populate the read-only array ds_lut on the stack but instead it
static. Also makes the object code smaller by 163 bytes:

Before:
text data bss dec hex filename
23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o

After:
text data bss dec hex filename
23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o
Heh.

@@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan
*chan) static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth
ds) {
u8 i;
- const enum dma_slave_buswidth ds_lut[] = {
+ static const enum dma_slave_buswidth ds_lut[] = {
DMA_SLAVE_BUSWIDTH_1_BYTE,
DMA_SLAVE_BUSWIDTH_2_BYTES,
DMA_SLAVE_BUSWIDTH_4_BYTES,
Array could be avoided altogether; you could check for power of two and then count bits. That would
give even shorter code, but I'm not sure about readability.
We might loose readability, Ill let Biju decide on this.

I'd also not mind using usual convention here: return int, >= 0 success, < 0 errno.
Agreed.

Cheers,
Prabhakar

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Pavel Machek
 

Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose),
which can later be merged once this patches have been merged.
And these are various minor nits I noticed while reviewing the code.
Thank you for the review. Do you want me to collate the changes and
submit or do you plan to submit them?
I'd preffer you to submit them.

Thank you,
Pavel


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Lad Prabhakar
 

Hi Pavel,

-----Original Message-----
From: Pavel Machek <pavel@denx.de>
Sent: 22 December 2021 10:06
To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
<pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose),
which can later be merged once this patches have been merged.
And these are various minor nits I noticed while reviewing the code.
Thank you for the review. Do you want me to collate the changes and submit or do you plan to submit them?

Cheers,
Prabhakar

Best regards,
Pavel

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index ef68dabcf4dc3..dacf43ed6d040 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya
+++ ml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/G2L combined pin and GPIO controller

maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
- The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+ The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function diff --git
a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ee2872e7d64c6..6946dd0d0485d 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -25,7 +25,7 @@
#include "../dmaengine.h"
#include "../virt-dma.h"

-enum rz_dmac_prep_type {
+enum rz_dmac_prep_type {
RZ_DMAC_DESC_MEMCPY,
RZ_DMAC_DESC_SLAVE_SG,
};
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 20b2af889ca96..08d0bf139ba3a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
psel_val[i] = MUX_FUNC(value);
}

- /* Register a single pin group listing all the pins we read from DT */
+ /* Register a single pin group, listing all the pins we read from DT
+*/
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
if (gsel < 0) {
ret = gsel;
@@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
if (ret)
return ret;

- /* Check config matching between to pin */
+ /* Check config matching between the pins */
if (i && prev_config != *config)
return -EOPNOTSUPP;

@@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), };

-static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
+static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, @@ -1109,7 +1109,7 @@ static int
rzg2l_pinctrl_probe(struct platform_device *pdev)
pctrl->clk = devm_clk_get(pctrl->dev, NULL);
if (IS_ERR(pctrl->clk)) {
ret = PTR_ERR(pctrl->clk);
- dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
+ dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret);
return ret;
}

@@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
pctrl->clk);
if (ret) {
dev_err(pctrl->dev,
- "failed to register GPIO clk disable action, %i\n",
+ "failed to register GPIO clk disable action: %i\n",
ret);
return ret;
}
@@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void) core_initcall(rzg2l_pinctrl_init);

MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
-MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
+MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family");
MODULE_LICENSE("GPL v2");


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Pavel Machek
 

Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
And these are various minor nits I noticed while reviewing the code.

Best regards,
Pavel

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index ef68dabcf4dc3..dacf43ed6d040 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/G2L combined pin and GPIO controller

maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
- The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+ The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index ee2872e7d64c6..6946dd0d0485d 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -25,7 +25,7 @@
#include "../dmaengine.h"
#include "../virt-dma.h"

-enum rz_dmac_prep_type {
+enum rz_dmac_prep_type {
RZ_DMAC_DESC_MEMCPY,
RZ_DMAC_DESC_SLAVE_SG,
};
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 20b2af889ca96..08d0bf139ba3a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
psel_val[i] = MUX_FUNC(value);
}

- /* Register a single pin group listing all the pins we read from DT */
+ /* Register a single pin group, listing all the pins we read from DT */
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
if (gsel < 0) {
ret = gsel;
@@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
if (ret)
return ret;

- /* Check config matching between to pin */
+ /* Check config matching between the pins */
if (i && prev_config != *config)
return -EOPNOTSUPP;

@@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
};

-static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
+static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
@@ -1109,7 +1109,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
pctrl->clk = devm_clk_get(pctrl->dev, NULL);
if (IS_ERR(pctrl->clk)) {
ret = PTR_ERR(pctrl->clk);
- dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
+ dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret);
return ret;
}

@@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
pctrl->clk);
if (ret) {
dev_err(pctrl->dev,
- "failed to register GPIO clk disable action, %i\n",
+ "failed to register GPIO clk disable action: %i\n",
ret);
return ret;
}
@@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void)
core_initcall(rzg2l_pinctrl_init);

MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
-MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
+MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family");
MODULE_LICENSE("GPL v2");


--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static

Pavel Machek
 

Hi!

commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream.

Don't populate the read-only array ds_lut on the stack but instead it
static. Also makes the object code smaller by 163 bytes:

Before:
text data bss dec hex filename
23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o

After:
text data bss dec hex filename
23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o
Heh.

@@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan *chan)
static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds)
{
u8 i;
- const enum dma_slave_buswidth ds_lut[] = {
+ static const enum dma_slave_buswidth ds_lut[] = {
DMA_SLAVE_BUSWIDTH_1_BYTE,
DMA_SLAVE_BUSWIDTH_2_BYTES,
DMA_SLAVE_BUSWIDTH_4_BYTES,
Array could be avoided altogether; you could check for power of two
and then count bits. That would give even shorter code, but I'm not
sure about readability.

I'd also not mind using usual convention here: return int, >= 0
success, < 0 errno.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver

Pavel Machek
 

Hi!

Add support for pin and gpio controller driver for RZ/G2L SoC.

Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>.
+static int rzg2l_map_add_config(struct pinctrl_map *map,
+ const char *group_or_pin,
+ enum pinctrl_map_type type,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ unsigned long *cfgs;
+
+ cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
+ GFP_KERNEL);
Should we check for overflows here, too?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl

Pavel Machek
 

Hi!

commit 7958f88aa6636f1927513c887a00e83168f12e35 upstream.

Add device tree binding documentation and header file for Renesas
RZ/G2L pinctrl.

+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+ power-source:
+ enum: [ 1800, 2500, 3300 ]
These are likely milliamps and millivolts, right? Elsewhere in device
trees microvolts and microamps are used, so that is not too
consistent.

Is the unit mentioned somewhere / should it be?

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Pavel Machek
 

On Wed 2021-12-22 01:22:09, nobuhiro1.iwamatsu@toshiba.co.jp wrote:
Hi all,

Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
Series looks okay to me. All I could find are
whitespaces/comments/documentation issues.

I'll proceed with testing; I can apply it if it passes and there are
no other comments.
I reviewed this series, there was no issue.
And build test was all green.
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/433945722
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Thank you, applied.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Nobuhiro Iwamatsu
 

Hi all,

Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
Series looks okay to me. All I could find are
whitespaces/comments/documentation issues.

I'll proceed with testing; I can apply it if it passes and there are
no other comments.
I reviewed this series, there was no issue.
And build test was all green.
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/433945722
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Best regards,
Nobuhiro

________________________________________
差出人: Pavel Machek
送信: 2021 12 月 21 日 (火曜日) 18:42
宛先: Lad Prabhakar
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT); Pavel Machek; Biju Das
件名: Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic


Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
Series looks okay to me. All I could find are
whitespaces/comments/documentation issues.

I'll proceed with testing; I can apply it if it passes and there are
no other comments.

Best regards,
                                                                Pavel
--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: 5.10.85 breaks CIP testing Re: [PATCH 5.10 00/33] 5.10.86-rc1 review

Nobuhiro Iwamatsu
 

Hi,

We should do what our users are likely to do... they want stable
kernel, and will not update toolchain in middle of product
maintainance. [Updating toolchain when starting new product with given
-cip kernel is more likely].

I believe that means we should stick to specific version, but I'm not
sure what version it is. We support Debian distro, likely gcc version
from that distro would be a good option? Perhaps we should ask on TSC
meeting tommorow?
Yes, we recommend using GCC with the rootfs environment.
And weare using the same container at compile time.


5.10 kernel was released in Dec 2020. At that time, gcc 8 and 9 were
maintained, and gcc 10 was new (https://gcc.gnu.org/releases.html).

To get some results for -stable testing, easiest options might be to
disable gcc plugin support in Kconfig.
+1.
Also, I think that this will not be necessary by preparing a build container
that matches the kernel.

Best regards,
Nobuhiro
________________________________________
差出人: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> が Pavel Machek <pavel@denx.de> の代理で送信
送信日時: 2021年12月20日 18:58
宛先: Chris Paterson
CC: Pavel Machek; cip-dev@lists.cip-project.org
件名: Re: [cip-dev] 5.10.85 breaks CIP testing Re: [PATCH 5.10 00/33] 5.10.86-rc1 review

Hi!

I believe we should not change build requirements in the middle of
stable series.

To our testing team: 5.10.85 introduced new requirements for the
build. gmp.h is now required in our configs, and maybe something else.
Hi Pavel, sorry for missing this email before now.
I can look into supporting this, depending on the answers to the comments below...
Thank you.

Easiest fix might be to add

# CONFIG_GCC_PLUGINS is not set

to our configs. Alternatively I know which patch to revert.

But I believe -stable should be the one doing the revert, as the patch
does not fix serious bug and introduces problem. Faster compile is
nice but let mainline have those kind of changes.
But that commit is needed to get gcc11 plugins to work with the 5.10.y
kernel tree. So either we "break" it for old and obsolete gcc versions
(i.e. gcc7), or newer supported versions break.
Well this leads us to an interesting point.
At the moment we use GCC v8.1.0 for building all of our kernel trees (cip & stable).
What does CIP want to do mid/long term? Keep upgrading the version we use? Or try and support a specific version of GCC for 10 years?
If the former, when do we want to upgrade?
If the latter, which version?
We should do what our users are likely to do... they want stable
kernel, and will not update toolchain in middle of product
maintainance. [Updating toolchain when starting new product with given
-cip kernel is more likely].

I believe that means we should stick to specific version, but I'm not
sure what version it is. We support Debian distro, likely gcc version
from that distro would be a good option? Perhaps we should ask on TSC
meeting tommorow?

5.10 kernel was released in Dec 2020. At that time, gcc 8 and 9 were
maintained, and gcc 10 was new (https://gcc.gnu.org/releases.html).

To get some results for -stable testing, easiest options might be to
disable gcc plugin support in Kconfig.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic

Pavel Machek
 

Hi!

This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.

All the patches have been cherry picked from v5.16-rc5.

I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
Series looks okay to me. All I could find are
whitespaces/comments/documentation issues.

I'll proceed with testing; I can apply it if it passes and there are
no other comments.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Re: 5.10.85 breaks CIP testing Re: [PATCH 5.10 00/33] 5.10.86-rc1 review

Jan Kiszka
 

On 20.12.21 10:58, Pavel Machek wrote:
Hi!

I believe we should not change build requirements in the middle of
stable series.

To our testing team: 5.10.85 introduced new requirements for the
build. gmp.h is now required in our configs, and maybe something else.
Hi Pavel, sorry for missing this email before now.
I can look into supporting this, depending on the answers to the comments below...
Thank you.

Easiest fix might be to add

# CONFIG_GCC_PLUGINS is not set

to our configs. Alternatively I know which patch to revert.

But I believe -stable should be the one doing the revert, as the patch
does not fix serious bug and introduces problem. Faster compile is
nice but let mainline have those kind of changes.
But that commit is needed to get gcc11 plugins to work with the 5.10.y
kernel tree. So either we "break" it for old and obsolete gcc versions
(i.e. gcc7), or newer supported versions break.
Well this leads us to an interesting point.
At the moment we use GCC v8.1.0 for building all of our kernel trees (cip & stable).
What does CIP want to do mid/long term? Keep upgrading the version we use? Or try and support a specific version of GCC for 10 years?
If the former, when do we want to upgrade?
If the latter, which version?
We should do what our users are likely to do... they want stable
kernel, and will not update toolchain in middle of product
maintainance. [Updating toolchain when starting new product with given
-cip kernel is more likely].

I believe that means we should stick to specific version, but I'm not
sure what version it is. We support Debian distro, likely gcc version
from that distro would be a good option? Perhaps we should ask on TSC
meeting tommorow?

5.10 kernel was released in Dec 2020. At that time, gcc 8 and 9 were
maintained, and gcc 10 was new (https://gcc.gnu.org/releases.html).

To get some results for -stable testing, easiest options might be to
disable gcc plugin support in Kconfig.

Best regards,
Pavel
The natural pairing would be "buster/kernel 4.19/gcc-8" and
"bullseye/kernel 5.10/gcc-10", indeed.

I'm definitely not able to attend the TSC call tomorrow. If you want to
discuss this topic, someone would have to pick up the kernel WG
representation.

Jan


[PATCH 5.10.y-cip 22/22] arm64: defconfig: Enable RZ_DMAC

Lad Prabhakar
 

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 7e2aa15f5ec3a8294127673f186c83b4d87cde13 upstream.

Enable DMAC driver support for Renesas RZ/G2L based platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210920093605.8906-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e022d807c6d8..2604bcd75baa 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -850,6 +850,7 @@ CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_RCAR_DMAC=y
CONFIG_RENESAS_USB_DMAC=m
+CONFIG_RZ_DMAC=y
CONFIG_TI_K3_UDMA=y
CONFIG_TI_K3_UDMA_GLUE_LAYER=y
CONFIG_VFIO=y
--
2.17.1


[PATCH 5.10.y-cip 21/22] arm64: dts: renesas: r9a07g044: Add DMAC support

Lad Prabhakar
 

From: Biju Das <biju.das.jz@bp.renesas.com>

commit bcd5e5173740087515bf3a05894917d0d8f5779f upstream.

Add DMAC support to RZ/G2L SoC DT.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719092535.4474-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 6e9643c36229..7c83a8d39351 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -212,6 +212,42 @@
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
};

+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g044-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_DMAC_ARESETN>,
+ <&cpg R9A07G044_DMAC_RST_ASYNC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.17.1


[PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static

Lad Prabhakar
 

From: Colin Ian King <colin.king@canonical.com>

commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream.

Don't populate the read-only array ds_lut on the stack but instead it
static. Also makes the object code smaller by 163 bytes:

Before:
text data bss dec hex filename
23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o

After:
text data bss dec hex filename
23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o

(gcc version 11.2.0)

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210915112038.12407-1-colin.king@canonical.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/dma/sh/rz-dmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index d9f2cfef878e..ee2872e7d64c 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan *chan)
static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds)
{
u8 i;
- const enum dma_slave_buswidth ds_lut[] = {
+ static const enum dma_slave_buswidth ds_lut[] = {
DMA_SLAVE_BUSWIDTH_1_BYTE,
DMA_SLAVE_BUSWIDTH_2_BYTES,
DMA_SLAVE_BUSWIDTH_4_BYTES,
--
2.17.1

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